A Novel Semi-Custom Design Flow to Tackle the Influence of Wires in Deep Sub-Micron Technologies / Alaaeldin Mohamed AbdelRazek Medra

Supervisor: Rafik Guindi

Thesis (M.A.)—Nile University, Egypt, 2012 .

"Includes bibliographical references"

Contents:
Chapters:
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Future Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Physical Implementation . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. Conventional Standard Cell Flow . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Circuit Description and RTL Simulation . . . . . . . . . . . . . . . 9
2.3 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.1 Analysis and Elaboration . . . . . . . . . . . . . . . . . . . 11
2.3.2 Setting Design Environment and Constraints . . . . . . . . 12
2.3.3 Defining Optimization Settings . . . . . . . . . . . . . . . . 14
2.3.4 Mapping and Optimization . . . . . . . . . . . . . . . . . . 15
2.3.5 Initial Placement and Routing and Incremental Optimization 16
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2.3.6 Output Generation . . . . . . . . . . . . . . . . . . . . . . . 16
2.4 Post Synthesis Verification . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.1 Timing and Area . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4.2 Gate Level Simulation . . . . . . . . . . . . . . . . . . . . . 19
2.4.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . 20
2.5 Automatic Placement and Routing . . . . . . . . . . . . . . . . . . 22
2.5.1 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.5.2 Floorplanning and Macro Placement . . . . . . . . . . . . . 24
2.5.3 Power Planning . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.4 Special Routing . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.5 Standard Cells Placement . . . . . . . . . . . . . . . . . . . 26
2.5.6 Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . 27
2.5.7 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.6 Post-Layout Verification . . . . . . . . . . . . . . . . . . . . . . . 29
2.6.1 Design Rule checking . . . . . . . . . . . . . . . . . . . . . . 29
2.6.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6.3 Gate Level Simulation . . . . . . . . . . . . . . . . . . . . . 30
2.6.4 Power Calculations . . . . . . . . . . . . . . . . . . . . . . . 30
2.7 Problems in Deep Sub-Micron Technologies . . . . . . . . . . . . . 30
3. Proposed Semi-Custom Design Flow . . . . . . . . . . . . . . . . . . . . 32
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Background on Bit-Sliced Data-Path . . . . . . . . . . . . . . . . . 33
3.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Structured Data Path (SDP) . . . . . . . . . . . . . . . . . . . . . 38
3.4.1 SDP File Format . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.2 SDP File Generation . . . . . . . . . . . . . . . . . . . . . . 42
3.5 Proposed Semi-custom Design Flow . . . . . . . . . . . . . . . . . . 44
3.5.1 Circuit Structure Description . . . . . . . . . . . . . . . . . 45
3.5.2 Relative Placement Constraints . . . . . . . . . . . . . . . . 47
3.5.3 Routing Constraints . . . . . . . . . . . . . . . . . . . . . . 48
3.5.4 Gate-Level Net-list Generation . . . . . . . . . . . . . . . . 49
3.5.5 Post Synthesis Verification . . . . . . . . . . . . . . . . . . . 50
3.5.6 Placement and Routing . . . . . . . . . . . . . . . . . . . . 50
3.5.7 Post Layout Verification . . . . . . . . . . . . . . . . . . . 52
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4. Application Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.1 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.2 Processor Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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4.2.1 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.2.2 Cluster Level . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2.3 Engine and Slice Level . . . . . . . . . . . . . . . . . . . . . 59
4.2.4 Unit Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5. Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.1.1 Technology Libraries . . . . . . . . . . . . . . . . . . . . . . 65
5.1.2 Operating Conditions and Constraints . . . . . . . . . . . . 65
5.2 Conventional Standard Cell Flow . . . . . . . . . . . . . . . . . . . 66
5.3 Proposed Semi-Custom Design Flow . . . . . . . . . . . . . . . . . 68
5.4 Results in Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 74
6. Conclusion and Future work . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2.1 Netlist Optimization . . . . . . . . . . . . . . . . . . . . . . 78
6.2.2 Flop Clustering . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.3 Future Technology Nodes . . . . . . . . . . . . . . . . . . . 80
Bibliography . . . . . . . . . . . . . . . . . . . .

Abstract:
Technology scaling has been the key enabler for the reduction of the area and power
of a chip over the past decades. However, layout structures are becoming tinier, and
hence more undesired physical effects occur. One of these undesired effects is the
increasing influence of interconnects. In the past, the performance, area and power
of a chip were dominated by transistors. Nevertheless, in Deep Deep Sub-Micron
(DDSM), i.e. 28 nm and below, this is no longer the case. Due to the ever increasing
dominance of interconnects on performance; the traditional standard-cell design flow
is not efficient, especially when the design is data-path intensive. Full-custom design
can cope with the fore mentioned interconnects issues, but the high design time is
hardly affordable. A feasible compromise is a semi-custom design.
A novel semi-custom design flow is proposed targeting designs which are datapath
intensive. It requires good knowledge of the architecture and only focuses on
the critical interconnect-dominated data-path components in the processor platform.
In this flow, the cells are placed manually to achieve high regularity in the data-path.
Based on the architecture and the data flow, the cells are placed in rows and columns
regularly abutted to each other. The data flow is going horizontally and the control
is going vertically. The goal is to optimize the most active wires to get shorter wires
which in turn will lead to lower RC and hence lower delays for high performance.
Moreover, reducing the wires’ lengths will reduce the number of buffers needed and
the switching capacitance. As a result, lower power consumption is obtained.
In the scope of this thesis, a semi-custom design flow is proposed in order to tackle
the influence of wires on the design’s power and delay in DDSM technologies. The flow
exploits Structure Data Path (SDP) to place the cells in rows and columns. Moreover,
the cells’ order within the same row leverages on an adopted linear ordering algorithm
in order to reduce the wires’ length and congestion. In order to test the proposed
flow, a gate-level implementation to one of the state-of-the-art processors proposed
by IMEC is performed. Finally, the results are compared to the conventional design
flow. The results, which are based on the 65 nm low power TSMC technology, have
shown a good potential to reduce wires’ length and congestion and hence reduce the
power consumed in charging and discharging the wires. The proposed flow achieves
17.48 % reduction in number of vias and 13.22 % reduction in total wire length and
a reduction of 25 % in the switching power and 10 % in the total power.

Text in English, abstracts in English.