MARC details
| 000 -LEADER |
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| fixed length control field |
08888nam a22002537a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
210215b2012 a|||f mb|| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
EG-CaNU |
| Transcribing agency |
EG-CaNU |
| 041 0# - Language Code |
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| Language code of text |
eng |
| Language code of abstract |
eng |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621 |
| 100 0# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Alaaeldin Mohamed AbdelRazek Medra |
| 245 1# - TITLE STATEMENT |
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| Title |
A Novel Semi-Custom Design Flow to Tackle the Influence of Wires in Deep Sub-Micron Technologies / |
| Statement of responsibility, etc. |
Alaaeldin Mohamed AbdelRazek Medra |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
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| Date of publication, distribution, etc. |
2012 |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
99 p. |
| Other physical details |
ill. |
| Dimensions |
21 cm. |
| 500 ## - GENERAL NOTE |
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| Materials specified |
Supervisor: Rafik Guindi |
| 502 ## - Dissertation Note |
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| Dissertation type |
Thesis (M.A.)—Nile University, Egypt, 2012 . |
| 504 ## - Bibliography |
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| Bibliography |
"Includes bibliographical references" |
| 505 0# - Contents |
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| Formatted contents note |
Contents:<br/>Chapters:<br/>1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1<br/>1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1<br/>1.2 Future Architectures . . . . . . . . . . . . . . . . . . . . . . . . . 3<br/>1.3 Physical Implementation . . . . . . . . . . . . . . . . . . . . . . . . 4<br/>1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 7<br/>2. Conventional Standard Cell Flow . . . . . . . . . . . . . . . . . . . . . . 8<br/>2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8<br/>2.2 Circuit Description and RTL Simulation . . . . . . . . . . . . . . . 9<br/>2.3 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10<br/>2.3.1 Analysis and Elaboration . . . . . . . . . . . . . . . . . . . 11<br/>2.3.2 Setting Design Environment and Constraints . . . . . . . . 12<br/>2.3.3 Defining Optimization Settings . . . . . . . . . . . . . . . . 14<br/>2.3.4 Mapping and Optimization . . . . . . . . . . . . . . . . . . 15<br/>2.3.5 Initial Placement and Routing and Incremental Optimization 16<br/>viii<br/>2.3.6 Output Generation . . . . . . . . . . . . . . . . . . . . . . . 16<br/>2.4 Post Synthesis Verification . . . . . . . . . . . . . . . . . . . . . . . 17<br/>2.4.1 Timing and Area . . . . . . . . . . . . . . . . . . . . . . . . 17<br/>2.4.2 Gate Level Simulation . . . . . . . . . . . . . . . . . . . . . 19<br/>2.4.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . 20<br/>2.5 Automatic Placement and Routing . . . . . . . . . . . . . . . . . . 22<br/>2.5.1 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . 22<br/>2.5.2 Floorplanning and Macro Placement . . . . . . . . . . . . . 24<br/>2.5.3 Power Planning . . . . . . . . . . . . . . . . . . . . . . . . . 25<br/>2.5.4 Special Routing . . . . . . . . . . . . . . . . . . . . . . . . . 25<br/>2.5.5 Standard Cells Placement . . . . . . . . . . . . . . . . . . . 26<br/>2.5.6 Clock Tree Synthesis . . . . . . . . . . . . . . . . . . . . . . 27<br/>2.5.7 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28<br/>2.6 Post-Layout Verification . . . . . . . . . . . . . . . . . . . . . . . 29<br/>2.6.1 Design Rule checking . . . . . . . . . . . . . . . . . . . . . . 29<br/>2.6.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29<br/>2.6.3 Gate Level Simulation . . . . . . . . . . . . . . . . . . . . . 30<br/>2.6.4 Power Calculations . . . . . . . . . . . . . . . . . . . . . . . 30<br/>2.7 Problems in Deep Sub-Micron Technologies . . . . . . . . . . . . . 30<br/>3. Proposed Semi-Custom Design Flow . . . . . . . . . . . . . . . . . . . . 32<br/>3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32<br/>3.2 Background on Bit-Sliced Data-Path . . . . . . . . . . . . . . . . . 33<br/>3.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33<br/>3.4 Structured Data Path (SDP) . . . . . . . . . . . . . . . . . . . . . 38<br/>3.4.1 SDP File Format . . . . . . . . . . . . . . . . . . . . . . . 38<br/>3.4.2 SDP File Generation . . . . . . . . . . . . . . . . . . . . . . 42<br/>3.5 Proposed Semi-custom Design Flow . . . . . . . . . . . . . . . . . . 44<br/>3.5.1 Circuit Structure Description . . . . . . . . . . . . . . . . . 45<br/>3.5.2 Relative Placement Constraints . . . . . . . . . . . . . . . . 47<br/>3.5.3 Routing Constraints . . . . . . . . . . . . . . . . . . . . . . 48<br/>3.5.4 Gate-Level Net-list Generation . . . . . . . . . . . . . . . . 49<br/>3.5.5 Post Synthesis Verification . . . . . . . . . . . . . . . . . . . 50<br/>3.5.6 Placement and Routing . . . . . . . . . . . . . . . . . . . . 50<br/>3.5.7 Post Layout Verification . . . . . . . . . . . . . . . . . . . 52<br/>3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52<br/>4. Application Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54<br/>4.1 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 54<br/>4.2 Processor Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . 56<br/>ix<br/>4.2.1 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 56<br/>4.2.2 Cluster Level . . . . . . . . . . . . . . . . . . . . . . . . . . 57<br/>4.2.3 Engine and Slice Level . . . . . . . . . . . . . . . . . . . . . 59<br/>4.2.4 Unit Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59<br/>5. Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64<br/>5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 64<br/>5.1.1 Technology Libraries . . . . . . . . . . . . . . . . . . . . . . 65<br/>5.1.2 Operating Conditions and Constraints . . . . . . . . . . . . 65<br/>5.2 Conventional Standard Cell Flow . . . . . . . . . . . . . . . . . . . 66<br/>5.3 Proposed Semi-Custom Design Flow . . . . . . . . . . . . . . . . . 68<br/>5.4 Results in Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 74<br/>6. Conclusion and Future work . . . . . . . . . . . . . . . . . . . . . . . . . 77<br/>6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77<br/>6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78<br/>6.2.1 Netlist Optimization . . . . . . . . . . . . . . . . . . . . . . 78<br/>6.2.2 Flop Clustering . . . . . . . . . . . . . . . . . . . . . . . . . 79<br/>6.2.3 Future Technology Nodes . . . . . . . . . . . . . . . . . . . 80<br/>Bibliography . . . . . . . . . . . . . . . . . . . . |
| 520 3# - Abstract |
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| Abstract |
Abstract:<br/>Technology scaling has been the key enabler for the reduction of the area and power<br/>of a chip over the past decades. However, layout structures are becoming tinier, and<br/>hence more undesired physical effects occur. One of these undesired effects is the<br/>increasing influence of interconnects. In the past, the performance, area and power<br/>of a chip were dominated by transistors. Nevertheless, in Deep Deep Sub-Micron<br/>(DDSM), i.e. 28 nm and below, this is no longer the case. Due to the ever increasing<br/>dominance of interconnects on performance; the traditional standard-cell design flow<br/>is not efficient, especially when the design is data-path intensive. Full-custom design<br/>can cope with the fore mentioned interconnects issues, but the high design time is<br/>hardly affordable. A feasible compromise is a semi-custom design.<br/>A novel semi-custom design flow is proposed targeting designs which are datapath<br/>intensive. It requires good knowledge of the architecture and only focuses on<br/>the critical interconnect-dominated data-path components in the processor platform.<br/>In this flow, the cells are placed manually to achieve high regularity in the data-path.<br/>Based on the architecture and the data flow, the cells are placed in rows and columns<br/>regularly abutted to each other. The data flow is going horizontally and the control<br/>is going vertically. The goal is to optimize the most active wires to get shorter wires<br/>which in turn will lead to lower RC and hence lower delays for high performance.<br/>Moreover, reducing the wires’ lengths will reduce the number of buffers needed and<br/>the switching capacitance. As a result, lower power consumption is obtained.<br/>In the scope of this thesis, a semi-custom design flow is proposed in order to tackle<br/>the influence of wires on the design’s power and delay in DDSM technologies. The flow<br/>exploits Structure Data Path (SDP) to place the cells in rows and columns. Moreover,<br/>the cells’ order within the same row leverages on an adopted linear ordering algorithm<br/>in order to reduce the wires’ length and congestion. In order to test the proposed<br/>flow, a gate-level implementation to one of the state-of-the-art processors proposed<br/>by IMEC is performed. Finally, the results are compared to the conventional design<br/>flow. The results, which are based on the 65 nm low power TSMC technology, have<br/>shown a good potential to reduce wires’ length and congestion and hence reduce the<br/>power consumed in charging and discharging the wires. The proposed flow achieves<br/>17.48 % reduction in number of vias and 13.22 % reduction in total wire length and<br/>a reduction of 25 % in the switching power and 10 % in the total power. |
| 546 ## - Language Note |
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| Language Note |
Text in English, abstracts in English. |
| 650 #4 - Subject |
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| Subject |
MSD |
| 655 #7 - Index Term-Genre/Form |
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| Source of term |
NULIB |
| focus term |
Dissertation, Academic |
| 690 ## - Subject |
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| School |
MSD |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Thesis |
| 650 #4 - Subject |
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| -- |
317 |
| 655 #7 - Index Term-Genre/Form |
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| -- |
187 |
| 690 ## - Subject |
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| -- |
317 |