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System-on-chip test architectures : nanometer design for testability / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.

Contributor(s): Material type: TextTextPublication details: Amsterdam ; Boston : Morgan Kaufmann Publishers, c2008.Description: xxxvi, 856 p. : ill. ; 25 cmISBN:
  • 9780123739735
  • 012373973X
Subject(s): DDC classification:
  • 621.395   22
Contents:
Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
Summary: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
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Holdings
Item type Current library Call number Copy number Status Date due Barcode
Books Books Main library General Stacks 621.395 / WA.S 2008 (Browse shelf(Opens below)) 1 Available 010977
Browsing Main library shelves, Shelving location: General Stacks Close shelf browser (Hides shelf browser)
621.395 / WA.D 2006 Digital design : 621.395 / WA.D 2006 Digital design : 621.395 / WA.E 2009 Electronic design automation : 621.395 / WA.S 2008 System-on-chip test architectures : 621.395 / WE.C 2005 CMOS VLSI design : 621.395 / WE.C 2005 CMOS VLSI design : 621.395 / WE.C 2005 CMOS VLSI design :

Includes bibliographical references and index.

Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

APPSCIE, NBK

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