MARC details
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
101202s2008 ne a b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2007023373 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780123739735 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
012373973X |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(Sirsi) u7757 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
EG-CaNU |
| Transcribing agency |
EG-CaNU |
| Modifying agency |
EG-CaNU |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
ncode |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
22 |
| 245 00 - TITLE STATEMENT |
|---|
| Title |
System-on-chip test architectures : |
| Remainder of title |
nanometer design for testability / |
| Statement of responsibility, etc. |
edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Amsterdam ; |
| -- |
Boston : |
| Name of publisher, distributor, etc. |
Morgan Kaufmann Publishers, |
| Date of publication, distribution, etc. |
c2008. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxxvi, 856 p. : |
| Other physical details |
ill. ; |
| Dimensions |
25 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. |
| 598 ## - |
|---|
| -- |
APPSCIE, NBK |
| 596 ## - |
|---|
| -- |
1 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Systems on a chip |
| General subdivision |
Testing. |
| 9 (RLIN) |
13931 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Testing. |
| 9 (RLIN) |
13932 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Design. |
| 9 (RLIN) |
13933 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Wang, Laung-Terng. |
| 9 (RLIN) |
240 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Stroud, Charles E. |
| 9 (RLIN) |
13934 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Touba, Nur A. |
| 9 (RLIN) |
13935 |