Ternary logic designs and In-Computing Ternary SRAM implementations using CNTFET/ Doaa Kamal Abdelrahman Hussein

Supervisor:
Ahmed G. Radwan

Thesis (M.A.)—Nile University, Egypt, 2023 .

"Includes bibliographical references"

Contents:
Contents
Page
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
Chapters:
1. Introduction 1
1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Thesis contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Literature Survey On Ternary Logic system and Ternary Circuits
implementation using CNTFET 4
2.1 Ternary logic system . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Ternary number representation . . . . . . . . . . . . . . . . . . . . . 6
2.2.1 Unsigned representation . . . . . . . . . . . . . . . . . . . . . 6
2.2.2 Signed representation . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Ternary logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
x

2.3.1 Ternary inverters and buffers . . . . . . . . . . . . . . . . . . 8
2.3.2 Ternary AND and OR gates . . . . . . . . . . . . . . . . . . . 9
2.4 Ternary logic circuits implementation . . . . . . . . . . . . . . . . . . 10
2.4.1 Carbon NanoTube Field Transistor (CNTFET) . . . . . . . . 10
2.4.2 Ternary basic logic gates implementation . . . . . . . . . . . . 13
2.4.3 Ternary logic circuits implementation . . . . . . . . . . . . . 17
2.4.4 Ternary arithmetic circuits implementation . . . . . . . . . . 17
2.5 Ternary SRAM implementation . . . . . . . . . . . . . . . . . . . . . 19
2.6 CNTFET Stanford Model . . . . . . . . . . . . . . . . . . . . . . . . 20
3. Comparative Study of CNTFET Implementations of 1-trit Multiplier 22
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Basic Ternary Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Ternary Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Ternary multiplexer . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 1-trit multiplier different designs . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Design-I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Design-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4 Simulation results and discussion . . . . . . . . . . . . . . . . . . . . 28
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4. Ternary SRAM Circuit Designs with CNTFETs 31
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.2 Ternary SRAM Designs . . . . . . . . . . . . . . . . . . . . . . . . . 33
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4.2.1 Design I: 6T-STI TSRAM . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Design II: 4T-STI TSRAM . . . . . . . . . . . . . . . . . . . . 33
4.2.3 Design III: 4T-binary based TSRAM . . . . . . . . . . . . . . 33
4.3 TSRAM designs simulation and comparison . . . . . . . . . . . . . . 35
4.3.1 Writing operation . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.2 Reading operation . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4 Stability and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4.1 Static Noise Margin (SNM) . . . . . . . . . . . . . . . . . . . 42
4.4.2 Impact of Soft Errors . . . . . . . . . . . . . . . . . . . . . . . 42
4.5 Results and discussion . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.1 Evaluation of The Static Noise Margin . . . . . . . . . . . . . 43
4.5.2 Evaluation of soft errors effect . . . . . . . . . . . . . . . . . . 44
4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5. Ternary In memory computational SRAM 48
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.2 Ternary SRAM Cicuit and Operation . . . . . . . . . . . . . . . . . . 49
5.3 Ternary In-Memory Computational SRAM implementation . . . . . . 49
5.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6. Conclusion and Future Work 54
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Abstract:
Ternary logic has become a promising alternative to traditional binary logic due to
achieving low power consumption and smaller chip area. Carbon nanotube field effect
transistor (CNTFET) is a promising technology as it achieves more advantages than
MOSFET due to its low off-current feature, low leakage power and threshold voltage
dependency on CNT diameter. Ternary logic circuits can be implemented easily
using CNTFET devices. The multiplier block is the most critical to the efficiency
and capability of the arithmetic systems, so the first part of our work is a comparison
of different 1-trit multiplier implementations using (VS-CNTFET) Stanford model.
The comparison is done in terms of area, power, and delay versus supply voltage
and temperature. Convolutional neural networks (CNNs) and artificial intelligence
(AI) are widely used in a variety of practical applications nowadays. The SRAM
block is a cornerstone, as it has high power consumption, wide space, and complexity.
Furthermore, the stability of the data in the SRAM against noise and performance
under radian exposure are major challenges in SRAM design. In our work, a proposed
design is presented concerning these challenges. In addition, complex CNN models
have massive data requirements and sophisticated data reuse patterns, causing several
hardware design issues. In-memory computational SRAM is a new technology for
computing directly in the memory blocks. Ternary in memory computational SRAM
(TIMC) is proposed and implemented.
viii

Keywords
Multiple-valued logic (MVL), ternary logic system, ternary logic gates, carbon nanotube field effect transistor (CNTFET), ternary multiplier, ternary SRAM, static
noise margin, soft errors, single event effect, amplitude-duration criterion, ternary in
memory computational SRAM.

Text in English, abstracts in English and Arabic