MARC details
| 000 -LEADER |
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| fixed length control field |
07002nam a22002537a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
201210b2023 a|||f bm|| 00| 0 eng d |
| 040 ## - CATALOGING SOURCE |
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| Original cataloging agency |
EG-CaNU |
| Transcribing agency |
EG-CaNU |
| 041 0# - Language Code |
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| Language code of text |
eng |
| Language code of abstract |
eng |
| -- |
ara |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621 |
| 100 0# - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Doaa Kamal Abdelrahman Hussein |
| 245 1# - TITLE STATEMENT |
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| Title |
Ternary logic designs and In-Computing Ternary SRAM implementations using CNTFET/ |
| Statement of responsibility, etc. |
Doaa Kamal Abdelrahman Hussein |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
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| Date of publication, distribution, etc. |
2023 |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
106 p. |
| Other physical details |
ill. |
| Dimensions |
21 cm. |
| 500 ## - GENERAL NOTE |
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| Materials specified |
Supervisor: <br/>Ahmed G. Radwan |
| 502 ## - Dissertation Note |
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| Dissertation type |
Thesis (M.A.)—Nile University, Egypt, 2023 . |
| 504 ## - Bibliography |
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| Bibliography |
"Includes bibliographical references" |
| 505 0# - Contents |
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| Formatted contents note |
Contents:<br/>Contents<br/>Page<br/>Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv<br/>Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii<br/>Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii<br/>Chapters:<br/>1. Introduction 1<br/>1.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . 1<br/>1.2 Thesis contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2<br/>1.3 Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3<br/>2. Literature Survey On Ternary Logic system and Ternary Circuits<br/>implementation using CNTFET 4<br/>2.1 Ternary logic system . . . . . . . . . . . . . . . . . . . . . . . . . . . 4<br/>2.2 Ternary number representation . . . . . . . . . . . . . . . . . . . . . 6<br/>2.2.1 Unsigned representation . . . . . . . . . . . . . . . . . . . . . 6<br/>2.2.2 Signed representation . . . . . . . . . . . . . . . . . . . . . . . 7<br/>2.3 Ternary logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7<br/>x<br/><br/>2.3.1 Ternary inverters and buffers . . . . . . . . . . . . . . . . . . 8<br/>2.3.2 Ternary AND and OR gates . . . . . . . . . . . . . . . . . . . 9<br/>2.4 Ternary logic circuits implementation . . . . . . . . . . . . . . . . . . 10<br/>2.4.1 Carbon NanoTube Field Transistor (CNTFET) . . . . . . . . 10<br/>2.4.2 Ternary basic logic gates implementation . . . . . . . . . . . . 13<br/>2.4.3 Ternary logic circuits implementation . . . . . . . . . . . . . 17<br/>2.4.4 Ternary arithmetic circuits implementation . . . . . . . . . . 17<br/>2.5 Ternary SRAM implementation . . . . . . . . . . . . . . . . . . . . . 19<br/>2.6 CNTFET Stanford Model . . . . . . . . . . . . . . . . . . . . . . . . 20<br/>3. Comparative Study of CNTFET Implementations of 1-trit Multiplier 22<br/>3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22<br/>3.2 Basic Ternary Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 22<br/>3.2.1 Ternary Decoder . . . . . . . . . . . . . . . . . . . . . . . . . 23<br/>3.2.2 Ternary multiplexer . . . . . . . . . . . . . . . . . . . . . . . . 23<br/>3.3 1-trit multiplier different designs . . . . . . . . . . . . . . . . . . . . . 25<br/>3.3.1 Design-I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br/>3.3.2 Design-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br/>3.4 Simulation results and discussion . . . . . . . . . . . . . . . . . . . . 28<br/>3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30<br/>4. Ternary SRAM Circuit Designs with CNTFETs 31<br/>4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31<br/>4.2 Ternary SRAM Designs . . . . . . . . . . . . . . . . . . . . . . . . . 33<br/>xi<br/><br/>4.2.1 Design I: 6T-STI TSRAM . . . . . . . . . . . . . . . . . . . . 33<br/>4.2.2 Design II: 4T-STI TSRAM . . . . . . . . . . . . . . . . . . . . 33<br/>4.2.3 Design III: 4T-binary based TSRAM . . . . . . . . . . . . . . 33<br/>4.3 TSRAM designs simulation and comparison . . . . . . . . . . . . . . 35<br/>4.3.1 Writing operation . . . . . . . . . . . . . . . . . . . . . . . . . 35<br/>4.3.2 Reading operation . . . . . . . . . . . . . . . . . . . . . . . . 38<br/>4.4 Stability and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . 42<br/>4.4.1 Static Noise Margin (SNM) . . . . . . . . . . . . . . . . . . . 42<br/>4.4.2 Impact of Soft Errors . . . . . . . . . . . . . . . . . . . . . . . 42<br/>4.5 Results and discussion . . . . . . . . . . . . . . . . . . . . . . . . . . 43<br/>4.5.1 Evaluation of The Static Noise Margin . . . . . . . . . . . . . 43<br/>4.5.2 Evaluation of soft errors effect . . . . . . . . . . . . . . . . . . 44<br/>4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47<br/>5. Ternary In memory computational SRAM 48<br/>5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48<br/>5.2 Ternary SRAM Cicuit and Operation . . . . . . . . . . . . . . . . . . 49<br/>5.3 Ternary In-Memory Computational SRAM implementation . . . . . . 49<br/>5.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . 52<br/>5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53<br/>6. Conclusion and Future Work 54<br/>Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 |
| 520 3# - Abstract |
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| Abstract |
Abstract:<br/>Ternary logic has become a promising alternative to traditional binary logic due to<br/>achieving low power consumption and smaller chip area. Carbon nanotube field effect<br/>transistor (CNTFET) is a promising technology as it achieves more advantages than<br/>MOSFET due to its low off-current feature, low leakage power and threshold voltage<br/>dependency on CNT diameter. Ternary logic circuits can be implemented easily<br/>using CNTFET devices. The multiplier block is the most critical to the efficiency<br/>and capability of the arithmetic systems, so the first part of our work is a comparison<br/>of different 1-trit multiplier implementations using (VS-CNTFET) Stanford model.<br/>The comparison is done in terms of area, power, and delay versus supply voltage<br/>and temperature. Convolutional neural networks (CNNs) and artificial intelligence<br/>(AI) are widely used in a variety of practical applications nowadays. The SRAM<br/>block is a cornerstone, as it has high power consumption, wide space, and complexity.<br/>Furthermore, the stability of the data in the SRAM against noise and performance<br/>under radian exposure are major challenges in SRAM design. In our work, a proposed<br/>design is presented concerning these challenges. In addition, complex CNN models<br/>have massive data requirements and sophisticated data reuse patterns, causing several<br/>hardware design issues. In-memory computational SRAM is a new technology for<br/>computing directly in the memory blocks. Ternary in memory computational SRAM<br/>(TIMC) is proposed and implemented.<br/>viii<br/><br/>Keywords<br/>Multiple-valued logic (MVL), ternary logic system, ternary logic gates, carbon nanotube field effect transistor (CNTFET), ternary multiplier, ternary SRAM, static<br/>noise margin, soft errors, single event effect, amplitude-duration criterion, ternary in<br/>memory computational SRAM. |
| 546 ## - Language Note |
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| Language Note |
Text in English, abstracts in English and Arabic |
| 650 #4 - Subject |
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| Subject |
MSD |
| 655 #7 - Index Term-Genre/Form |
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| Source of term |
NULIB |
| focus term |
Dissertation, Academic |
| 690 ## - Subject |
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| School |
MSD |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
Dewey Decimal Classification |
| Koha item type |
Thesis |
| 650 #4 - Subject |
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| -- |
317 |
| 655 #7 - Index Term-Genre/Form |
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187 |
| 690 ## - Subject |
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317 |