Automated Verilog-A Test Bench Generator with Focus on Novel Devices Modeling/ (Record no. 9187)

MARC details
000 -LEADER
fixed length control field 09596nam a22002537a 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 211216b2012 |||a|||f bm|| 00| 0 eng d
040 ## - CATALOGING SOURCE
Original cataloging agency EG-CaNU
Transcribing agency EG-CaNU
041 0# - Language Code
Language code of text eng
Language code of abstract eng
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621
100 0# - MAIN ENTRY--PERSONAL NAME
Personal name Mohamed Saeed Nassar
245 1# - TITLE STATEMENT
Title Automated Verilog-A Test Bench Generator with Focus on Novel Devices Modeling/
Statement of responsibility, etc. Mohamed Saeed Nassar
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2012
300 ## - PHYSICAL DESCRIPTION
Extent 123 p.
Other physical details ill.
Dimensions 21 cm.
500 ## - GENERAL NOTE
Materials specified Supervisor: Rafik Guindi
502 ## - Dissertation Note
Dissertation type Thesis (M.A.)—Nile University, Egypt, 2012 .
504 ## - Bibliography
Bibliography "Includes bibliographical references"
505 0# - Contents
Formatted contents note Contents:<br/>Chapter 1 Introduction ..................................................................................................................2<br/>1.1 Motivation ................................................................................................................. 2<br/>1.2 Overview .................................................................................................................... 3<br/>1.2.1 Design Flow ........................................................................................................... 3<br/>1.2.2 Functional Verification .......................................................................................... 7<br/>1.2.2.1 Digital Functional Verification ....................................................................... 7<br/>1.2.2.2 Analogue Functional Verification .................................................................. 9<br/>1.3 Task Description ...................................................................................................... 11<br/>Chapter 2 Background ................................................................................................................ 13<br/>2.1 Verilog-A Overview .................................................................................................. 13<br/>2.1.1 Module ................................................................................................................ 13<br/>2.2 SKILL Overview ........................................................................................................ 14<br/>2.2.1 Important Procedures: ......................................................................................... 15<br/>2.2.2 Important Skill Data Structures ........................................................................... 16<br/>2.2.2.1 Disembodied Property Lists ......................................................................... 17<br/>2.2.2.2 Association Tables ....................................................................................... 17<br/>2.3 Cadence Design Framework (DF II) Overview ......................................................... 17<br/>Chapter 3 Introduction to Memristors ....................................................................................... 19<br/>3.1 Introduction to Memristors ..................................................................................... 20<br/>3.2 Memristor Origin ..................................................................................................... 22<br/>3.3 Memristor Characteristics and Modelling ............................................................... 28<br/>3.4 Device Models ......................................................................................................... 32<br/>3.4.1 Linear Ion Drift Model.......................................................................................... 32<br/>3.4.2 KAUST Model ....................................................................................................... 37<br/>3.4.3 Non-Linear Ion Drift Model .................................................................................. 38<br/>3.4.4 Simmons Tunnel Barrier Model ........................................................................... 39<br/>3.4.5 Threshold Adaptive Memristor Model ................................................................. 42<br/>TABLE OF CONTENTS<br/>vii<br/>Chapter 4 Test Bench Generator Implementation ..................................................................... 44<br/>4.1 File Structure and Description ................................................................................. 44<br/>4.1.1 NuNiscTBGenMain ............................................................................................... 45<br/>4.1.2 NuNiscTBGenGui.................................................................................................. 46<br/>4.1.3 NuNiscTBGenParseVerA ...................................................................................... 51<br/>4.1.4 NuNiscTBGenMainBackEnd ................................................................................. 56<br/>4.1.4.1 NuNiscTBGenUpdatePinLists ....................................................................... 59<br/>4.1.4.2 NuNiscTBGenUpdateParamLists ................................................................. 59<br/>4.1.4.3 NuNiscTBGenInitADETemp .......................................................................... 59<br/>4.1.4.4 NuNiscTBGenAddNewView ......................................................................... 60<br/>4.1.4.5 NuNiscTBGenCreateSym ............................................................................. 60<br/>4.1.4.6 ahdlUpdateViewInfo .................................................................................... 65<br/>4.1.4.7 NuNiscTBGenCreateTermOrder .................................................................. 65<br/>4.1.4.8 NuNiscTBGenreateCDFParams .................................................................... 65<br/>4.1.4.9 NuNiscTBGenCreateSchem ......................................................................... 67<br/>4.1.4.10 NuNiscTBGenCreateADEState ................................................................. 79<br/>Chapter 5 Testing and Results .................................................................................................... 84<br/>5.1 Verilog-A Model Testing .......................................................................................... 84<br/>5.1.1 Test Methodology ................................................................................................ 84<br/>5.1.2 Test Results .......................................................................................................... 86<br/>5.1.2.1 Manual Test Bench Generation ................................................................... 86<br/>5.1.2.2 Automated Test Bench Generation ............................................................. 88<br/>5.2 Other Model Results ................................................................................................ 96<br/>5.3 Memristor Models Testing ...................................................................................... 98<br/>5.3.1 Methodology ....................................................................................................... 98<br/>5.3.1.1 Methodology 1 ............................................................................................ 98<br/>5.3.1.2 Methodology 2 ............................................................................................ 99<br/>viii<br/>5.3.1.3 Methodology 3 ............................................................................................ 99<br/>5.3.2 Model Results .................................................................................................... 100<br/>5.3.2.1 Linear Ion Drift Model Simulation Results ................................................. 100<br/>5.3.2.2 Simulation Results for the KAUST Model .................................................. 101<br/>5.3.2.3 Simulation Results of the Non-Linear Ion Drift Model .............................. 102<br/>5.3.2.4 Simulation Results for the Simmons Tunnel Barrier Model ...................... 103<br/>5.3.2.5 Simulation Results of the Threshold Adaptive Memristor Model ............. 104<br/>5.3.3 Comparison Between Different Models............................................................. 105<br/>Chapter 6 Conclusion and Future Work ................................................................................... 106<br/>References .................................................................................................................................. 108
520 3# - Abstract
Abstract Abstract:<br/>ABSTRACT<br/>ystem modelling and verification has always been a hard issue, especially when systems have increased complexity, compounded with the limited ability to verify the whole system at the transistor level or the extracted views. The user has to replace some system blocks with some behavioural models to be able to simulate the whole system. Verilog-A has proven to be a simple, efficient and accurate language to do the behavioural modelling and include as much or as little detail as the user wants.<br/>In the area of behavioural modelling of novel devices, Verilog-A has proven to be more computational efficient during the phases of developing first device models, because it enables the use of complex mathematical functions in a simulation friendly way, unlike SPICE for example.<br/>In this thesis, a completely in-house developed Verilog-A test bench generator tool is presented, which automatically creates test bench schematics under the Cadence® environment, and prepares the simulation environment to ease the process of model testing and parameterization for the user. Also, the tool has been used to parameterize, simulate, verify and analyse several novel memristor models.
546 ## - Language Note
Language Note Text in English, abstracts in English.
650 #4 - Subject
Subject MSD
655 #7 - Index Term-Genre/Form
Source of term NULIB
focus term Dissertation, Academic
690 ## - Subject
School MSD
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Thesis
650 #4 - Subject
-- 317
655 #7 - Index Term-Genre/Form
-- 187
690 ## - Subject
-- 317
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Main library Main library 12/16/2021   621/ M.S.A 2012 12/16/2021 12/16/2021 Thesis