Automated Verilog-A Test Bench Generator with Focus on Novel Devices Modeling/ Mohamed Saeed Nassar

Supervisor: Rafik Guindi

Thesis (M.A.)—Nile University, Egypt, 2012 .

"Includes bibliographical references"

Contents:
Chapter 1 Introduction ..................................................................................................................2
1.1 Motivation ................................................................................................................. 2
1.2 Overview .................................................................................................................... 3
1.2.1 Design Flow ........................................................................................................... 3
1.2.2 Functional Verification .......................................................................................... 7
1.2.2.1 Digital Functional Verification ....................................................................... 7
1.2.2.2 Analogue Functional Verification .................................................................. 9
1.3 Task Description ...................................................................................................... 11
Chapter 2 Background ................................................................................................................ 13
2.1 Verilog-A Overview .................................................................................................. 13
2.1.1 Module ................................................................................................................ 13
2.2 SKILL Overview ........................................................................................................ 14
2.2.1 Important Procedures: ......................................................................................... 15
2.2.2 Important Skill Data Structures ........................................................................... 16
2.2.2.1 Disembodied Property Lists ......................................................................... 17
2.2.2.2 Association Tables ....................................................................................... 17
2.3 Cadence Design Framework (DF II) Overview ......................................................... 17
Chapter 3 Introduction to Memristors ....................................................................................... 19
3.1 Introduction to Memristors ..................................................................................... 20
3.2 Memristor Origin ..................................................................................................... 22
3.3 Memristor Characteristics and Modelling ............................................................... 28
3.4 Device Models ......................................................................................................... 32
3.4.1 Linear Ion Drift Model.......................................................................................... 32
3.4.2 KAUST Model ....................................................................................................... 37
3.4.3 Non-Linear Ion Drift Model .................................................................................. 38
3.4.4 Simmons Tunnel Barrier Model ........................................................................... 39
3.4.5 Threshold Adaptive Memristor Model ................................................................. 42
TABLE OF CONTENTS
vii
Chapter 4 Test Bench Generator Implementation ..................................................................... 44
4.1 File Structure and Description ................................................................................. 44
4.1.1 NuNiscTBGenMain ............................................................................................... 45
4.1.2 NuNiscTBGenGui.................................................................................................. 46
4.1.3 NuNiscTBGenParseVerA ...................................................................................... 51
4.1.4 NuNiscTBGenMainBackEnd ................................................................................. 56
4.1.4.1 NuNiscTBGenUpdatePinLists ....................................................................... 59
4.1.4.2 NuNiscTBGenUpdateParamLists ................................................................. 59
4.1.4.3 NuNiscTBGenInitADETemp .......................................................................... 59
4.1.4.4 NuNiscTBGenAddNewView ......................................................................... 60
4.1.4.5 NuNiscTBGenCreateSym ............................................................................. 60
4.1.4.6 ahdlUpdateViewInfo .................................................................................... 65
4.1.4.7 NuNiscTBGenCreateTermOrder .................................................................. 65
4.1.4.8 NuNiscTBGenreateCDFParams .................................................................... 65
4.1.4.9 NuNiscTBGenCreateSchem ......................................................................... 67
4.1.4.10 NuNiscTBGenCreateADEState ................................................................. 79
Chapter 5 Testing and Results .................................................................................................... 84
5.1 Verilog-A Model Testing .......................................................................................... 84
5.1.1 Test Methodology ................................................................................................ 84
5.1.2 Test Results .......................................................................................................... 86
5.1.2.1 Manual Test Bench Generation ................................................................... 86
5.1.2.2 Automated Test Bench Generation ............................................................. 88
5.2 Other Model Results ................................................................................................ 96
5.3 Memristor Models Testing ...................................................................................... 98
5.3.1 Methodology ....................................................................................................... 98
5.3.1.1 Methodology 1 ............................................................................................ 98
5.3.1.2 Methodology 2 ............................................................................................ 99
viii
5.3.1.3 Methodology 3 ............................................................................................ 99
5.3.2 Model Results .................................................................................................... 100
5.3.2.1 Linear Ion Drift Model Simulation Results ................................................. 100
5.3.2.2 Simulation Results for the KAUST Model .................................................. 101
5.3.2.3 Simulation Results of the Non-Linear Ion Drift Model .............................. 102
5.3.2.4 Simulation Results for the Simmons Tunnel Barrier Model ...................... 103
5.3.2.5 Simulation Results of the Threshold Adaptive Memristor Model ............. 104
5.3.3 Comparison Between Different Models............................................................. 105
Chapter 6 Conclusion and Future Work ................................................................................... 106
References .................................................................................................................................. 108

Abstract:
ABSTRACT
ystem modelling and verification has always been a hard issue, especially when systems have increased complexity, compounded with the limited ability to verify the whole system at the transistor level or the extracted views. The user has to replace some system blocks with some behavioural models to be able to simulate the whole system. Verilog-A has proven to be a simple, efficient and accurate language to do the behavioural modelling and include as much or as little detail as the user wants.
In the area of behavioural modelling of novel devices, Verilog-A has proven to be more computational efficient during the phases of developing first device models, because it enables the use of complex mathematical functions in a simulation friendly way, unlike SPICE for example.
In this thesis, a completely in-house developed Verilog-A test bench generator tool is presented, which automatically creates test bench schematics under the Cadence® environment, and prepares the simulation environment to ease the process of model testing and parameterization for the user. Also, the tool has been used to parameterize, simulate, verify and analyse several novel memristor models.

Text in English, abstracts in English.