Efficient Scenario Based Testing Methodology Using Universal Verification Methodology / (Record no. 8930)

MARC details
000 -LEADER
fixed length control field 05733nam a22002537a 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 210221b2016 a|||f mb|| 00| 0 eng d
040 ## - CATALOGING SOURCE
Original cataloging agency EG-CaNU
Transcribing agency EG-CaNU
041 0# - Language Code
Language code of text eng
Language code of abstract eng
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621
100 0# - MAIN ENTRY--PERSONAL NAME
Personal name Khaled Fathy Kabil
245 1# - TITLE STATEMENT
Title Efficient Scenario Based Testing Methodology Using Universal Verification Methodology /
Statement of responsibility, etc. Khaled Fathy Kabil
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2016
300 ## - PHYSICAL DESCRIPTION
Extent 95 p.
Other physical details ill.
Dimensions 21 cm.
500 ## - GENERAL NOTE
Materials specified Supervisor: Rafik Guindi
502 ## - Dissertation Note
Dissertation type Thesis (M.A.)—Nile University, Egypt, 2016 .
504 ## - Bibliography
Bibliography "Includes bibliographical references"
505 0# - Contents
Formatted contents note Contents:<br/>1. INTRODUCTION ....................................................................................................... 1<br/>1.1 Verification................................................................................................ 1<br/>1.1.1 What is verified? ................................................................................ 1<br/>1.1.2 How it is verified? .............................................................................. 2<br/>1.2. Hardware verification language ................................................................ 3<br/>1.2.1. System Verilog................................................................................... 3<br/>1.2.2. System Verilog Test bench architecture ............................................ 3<br/>1.3. Verification methodologies and test benches ............................................ 7<br/>1.3.1. UVM test bench ................................................................................. 8<br/>1.4. Test Scenario library ............................................................................... 10<br/>2. Literature survey ........................................................................................................ 11<br/>2.1. General UVM topic ................................................................................. 12<br/>2.2. UVM in IP verification ........................................................................... 13<br/>2.3. UVM sequences and test scenarios ......................................................... 14<br/>2.3.1. UVM sequences ............................................................................... 14<br/>2.3.2. Graph based approaches scenarios ................................................... 27<br/>3. CORE OF THE WORK ............................................................................................ 33<br/>3.1. The Proposed Methodology .................................................................... 33<br/>vii<br/>3.2. Implementation........................................................................................ 38<br/>3.2.1. Single stream scenario class............................................................. 38<br/>3.2.2. Multi-stream scenario event barrier class ........................................ 45<br/>3.2.3. Multi stream scenario virtual sequence class ................................... 48<br/>4. RESULTS .................................................................................................................. 51<br/>4.1. Introduction ............................................................................................. 51<br/>4.2. Serial Flash IP ......................................................................................... 52<br/>4.2.1. Design .............................................................................................. 52<br/>4.2.2. Environment ..................................................................................... 53<br/>4.2.3. Results .............................................................................................. 57<br/>4.3. HMC IP ................................................................................................... 62<br/>4.3.1. Design .............................................................................................. 62<br/>4.3.2. Environment ..................................................................................... 64<br/>4.3.3. Results .............................................................................................. 68<br/>5. Conclusions and future work ..................................................................................... 70<br/>5.1. Conclusions ............................................................................................. 70<br/>5.2. Future work ............................................................................................. 72<br/>REFERENCES ...................................................
520 3# - Abstract
Abstract Abstract:<br/>Most of modern verification architects use randomness supported by system verilog (SV) to enable defining a generic path for a test to follow. This generic path stresses on a subset of features, and allows randomization to explore corners in depth. Setting up such test case requires a well-defined stimulus generation methodology that consumes less time to cover all the corner-cases. Moreover, Off-the-shelf scenario libraries, synchronization and scheduling process methodology for the parallel stimuli need to be reused across several test cases. In this paper, a novel methodology for creating test scenarios is proposed. Moreover, making use of object oriented principles to build composite layered scenario sequences with a generic parallel stimuli synchronization process is introduced. The proposed methodology is built as a generic library code to be reused in many designs. The results of applying this methodology on test cases show enhancements on reusability, test cases count, coverage closure and performance.
546 ## - Language Note
Language Note Text in English, abstracts in English.
650 #4 - Subject
Subject MSD
655 #7 - Index Term-Genre/Form
Source of term NULIB
focus term Dissertation, Academic
690 ## - Subject
School MSD
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Thesis
650 #4 - Subject
-- 317
655 #7 - Index Term-Genre/Form
-- 187
690 ## - Subject
-- 317
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Main library Main library 02/21/2021   621/ K.K.E 2016 02/21/2021 02/21/2021 Thesis