Efficient Scenario Based Testing Methodology Using Universal Verification Methodology /
Khaled Fathy Kabil
Efficient Scenario Based Testing Methodology Using Universal Verification Methodology / Khaled Fathy Kabil - 2016 - 95 p. ill. 21 cm.
Supervisor: Rafik Guindi
Thesis (M.A.)—Nile University, Egypt, 2016 .
"Includes bibliographical references"
Contents:
1. INTRODUCTION ....................................................................................................... 1
1.1 Verification................................................................................................ 1
1.1.1 What is verified? ................................................................................ 1
1.1.2 How it is verified? .............................................................................. 2
1.2. Hardware verification language ................................................................ 3
1.2.1. System Verilog................................................................................... 3
1.2.2. System Verilog Test bench architecture ............................................ 3
1.3. Verification methodologies and test benches ............................................ 7
1.3.1. UVM test bench ................................................................................. 8
1.4. Test Scenario library ............................................................................... 10
2. Literature survey ........................................................................................................ 11
2.1. General UVM topic ................................................................................. 12
2.2. UVM in IP verification ........................................................................... 13
2.3. UVM sequences and test scenarios ......................................................... 14
2.3.1. UVM sequences ............................................................................... 14
2.3.2. Graph based approaches scenarios ................................................... 27
3. CORE OF THE WORK ............................................................................................ 33
3.1. The Proposed Methodology .................................................................... 33
vii
3.2. Implementation........................................................................................ 38
3.2.1. Single stream scenario class............................................................. 38
3.2.2. Multi-stream scenario event barrier class ........................................ 45
3.2.3. Multi stream scenario virtual sequence class ................................... 48
4. RESULTS .................................................................................................................. 51
4.1. Introduction ............................................................................................. 51
4.2. Serial Flash IP ......................................................................................... 52
4.2.1. Design .............................................................................................. 52
4.2.2. Environment ..................................................................................... 53
4.2.3. Results .............................................................................................. 57
4.3. HMC IP ................................................................................................... 62
4.3.1. Design .............................................................................................. 62
4.3.2. Environment ..................................................................................... 64
4.3.3. Results .............................................................................................. 68
5. Conclusions and future work ..................................................................................... 70
5.1. Conclusions ............................................................................................. 70
5.2. Future work ............................................................................................. 72
REFERENCES ...................................................
Abstract:
Most of modern verification architects use randomness supported by system verilog (SV) to enable defining a generic path for a test to follow. This generic path stresses on a subset of features, and allows randomization to explore corners in depth. Setting up such test case requires a well-defined stimulus generation methodology that consumes less time to cover all the corner-cases. Moreover, Off-the-shelf scenario libraries, synchronization and scheduling process methodology for the parallel stimuli need to be reused across several test cases. In this paper, a novel methodology for creating test scenarios is proposed. Moreover, making use of object oriented principles to build composite layered scenario sequences with a generic parallel stimuli synchronization process is introduced. The proposed methodology is built as a generic library code to be reused in many designs. The results of applying this methodology on test cases show enhancements on reusability, test cases count, coverage closure and performance.
Text in English, abstracts in English.
MSD
Dissertation, Academic
621
Efficient Scenario Based Testing Methodology Using Universal Verification Methodology / Khaled Fathy Kabil - 2016 - 95 p. ill. 21 cm.
Supervisor: Rafik Guindi
Thesis (M.A.)—Nile University, Egypt, 2016 .
"Includes bibliographical references"
Contents:
1. INTRODUCTION ....................................................................................................... 1
1.1 Verification................................................................................................ 1
1.1.1 What is verified? ................................................................................ 1
1.1.2 How it is verified? .............................................................................. 2
1.2. Hardware verification language ................................................................ 3
1.2.1. System Verilog................................................................................... 3
1.2.2. System Verilog Test bench architecture ............................................ 3
1.3. Verification methodologies and test benches ............................................ 7
1.3.1. UVM test bench ................................................................................. 8
1.4. Test Scenario library ............................................................................... 10
2. Literature survey ........................................................................................................ 11
2.1. General UVM topic ................................................................................. 12
2.2. UVM in IP verification ........................................................................... 13
2.3. UVM sequences and test scenarios ......................................................... 14
2.3.1. UVM sequences ............................................................................... 14
2.3.2. Graph based approaches scenarios ................................................... 27
3. CORE OF THE WORK ............................................................................................ 33
3.1. The Proposed Methodology .................................................................... 33
vii
3.2. Implementation........................................................................................ 38
3.2.1. Single stream scenario class............................................................. 38
3.2.2. Multi-stream scenario event barrier class ........................................ 45
3.2.3. Multi stream scenario virtual sequence class ................................... 48
4. RESULTS .................................................................................................................. 51
4.1. Introduction ............................................................................................. 51
4.2. Serial Flash IP ......................................................................................... 52
4.2.1. Design .............................................................................................. 52
4.2.2. Environment ..................................................................................... 53
4.2.3. Results .............................................................................................. 57
4.3. HMC IP ................................................................................................... 62
4.3.1. Design .............................................................................................. 62
4.3.2. Environment ..................................................................................... 64
4.3.3. Results .............................................................................................. 68
5. Conclusions and future work ..................................................................................... 70
5.1. Conclusions ............................................................................................. 70
5.2. Future work ............................................................................................. 72
REFERENCES ...................................................
Abstract:
Most of modern verification architects use randomness supported by system verilog (SV) to enable defining a generic path for a test to follow. This generic path stresses on a subset of features, and allows randomization to explore corners in depth. Setting up such test case requires a well-defined stimulus generation methodology that consumes less time to cover all the corner-cases. Moreover, Off-the-shelf scenario libraries, synchronization and scheduling process methodology for the parallel stimuli need to be reused across several test cases. In this paper, a novel methodology for creating test scenarios is proposed. Moreover, making use of object oriented principles to build composite layered scenario sequences with a generic parallel stimuli synchronization process is introduced. The proposed methodology is built as a generic library code to be reused in many designs. The results of applying this methodology on test cases show enhancements on reusability, test cases count, coverage closure and performance.
Text in English, abstracts in English.
MSD
Dissertation, Academic
621