000			01866cam a2200289 a 4500
008			120710s2010 nyua b 001 0 eng
010			_a2010022678
020			_a9780071635196
020			_a007163519X
035			_a(Sirsi) u8351
040			_aEG-CaNU _cEG-CaNU _dEG-CaNU
042			_ancode
082	0	0	_a621.395 _2 22
100	1		_aKundu, Sandip. _915394
245	1	0	_aNanoscale CMOS VLSI circuits : _b design for manufacturability / _c Sandip Kundu, Aswin Sreedhar.
246	1	4	_aNanoscale complementary metal oxide semiconductor very large-scale integration circuits
260			_aNew York : _b McGraw-Hill, _c c2010.
300			_axv, 296 p. : _b ill. ; _c 24 cm.
504			_aIncludes bibliographical references and index.
505	0		_aSemiconductor manufacturing -- Process and device variability : analysis and modeling -- Manufacturing-aware physical design closure -- Metrology, manufacturing defects, and defect extraction -- Defect impact modeling and yield improvement techniques -- Physical design and reliability -- Design for manufacturability : tools and methodologies.
520			_aThis detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes, Nanoscale CMOS VLSI Circuits: Design for Manufacturability focuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource.
650		0	_aMetal oxide semiconductors, Complementary _x Design and construction. _915395
650		0	_aIntegrated circuits _x Very large scale integration _x Design and construction. _915396
650		0	_aNanoelectronics. _91939
700	1		_aSreedhar, Aswin. _915397
596			_a1
999			_c7254 _d7254