000			01662cam a2200265 a 4500
008			120528s2010 enka b 001 0 eng
010			_a2009042290
020			_a9780521872447
035			_a(Sirsi) u8210
040			_aEG-CaNU _c EG-CaNU _d EG-CaNU
042			_ancode
082	0	0	_a621.395 _2 22
100	1		_aBeerel, Peter A. _915018
245	1	2	_aA designer’s guide to asynchronous VLSI / _c Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti.
260			_aCambridge ; _a New York : _b Cambridge University Press, _c 2010.
300			_axii, 339 p. : _b ill. ; _c 26 cm.
504			_aIncludes bibliographical references and index.
505	0		_aIntroduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith.
520			_aThis book provides an introduction to this diverse area of VLSI from a designer’s point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future.
650		0	_aIntegrated circuits _x Very large scale integration _x Computer-aided design. _915019
650		0	_aIntegrated circuits _x Very large scale integration _x Design and construction. _915020
700	1		_aOzdag, Recep O. _915021
700	1		_aFerretti, Marcos. _915022
596			_a1
999			_c7110 _d7110