000 01563cam a22002771a 4500
008 100307s2005 ne a 000 0 eng
010 _a 2005299338
020 _a 0127518037
035 _a(Sirsi) u4402
040 _aEG-CaNU
_c EG-CaNU
_d EG-CaNU
042 _ancode
082 0 0 _a 621.381548
_2 22
100 1 _a Wile, Bruce.
_98777
245 1 0 _a Comprehensive functional verification the complete industry cycle /
_c Bruce Wile, John C. Goss, Wolfgang Roesner.
260 _aAmsterdam ;
_a Boston :
_b Elsevier/Morgan Kaufmann,
_c c2005.
300 _axxiii, 676 p. :
_b ill. ;
_c 24 cm.
504 _aIncludes bibliographical references (p. 657-662) and index.
505 _aVerification in the Chip Design Process -- Verification Flow -- Fundamentals of Simulation Based Verification -- The Verification Plan -- HDLs and Simulation Engines -- Creating Environments -- Strategies for Simulation based Stimulus Generation -- Strategies for Results Checking in Simulation Based Verification -- System Reset and Bring-up -- Re-Use Strategies and System Simulation -- Completing the Verification Cycle -- Advanced Verification Techniques.
650 0 _aIntegrated circuits
_x Verification.
_98778
650 0 _aComputer engineering.
_98779
700 1 _aGoss, John C.
_98780
700 1 _aRoesner, W.
_q (Wolfgang)
_98781
596 _a1
999 _c3409
_d3409