000			08782nam a22002657a 4500
008			201210b2024 a|||f bm|| 00| 0 eng d
024	7		_a0009-0009-2269-0800 _2ORCID
040			_aEG-CaNU _cEG-CaNU
041	0		_aeng _beng _bara
082			_a621
100	0		_aAmr Ali Mahmoud Mohammaden _93231
245	1		_aDesign and implementation of ternary systems using CNTFET _c/Amr Ali Mahmoud Mohammaden
260			_c2024
300			_a83 p. _bill. _c21 cm.
500			_3Supervisor: Ahmed Gomaa Radwan
502			_aThesis (MS.c)—Nile University, Egypt, 2024.
504			_a"Includes bibliographical references"
505	0		_aContents: Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Chapters: 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Literature Survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 MVL Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 Ternary Number Representations . . . . . . . . . . . . . . . 6 2.1.2 Signed and Unsigned Representation . . . . . . . . . . . . . 7 2.1.3 Ternary Arithmetic Operations . . . . . . . . . . . . . . . . 10 2.1.4 Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.5 Logic Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.6 Carbon Nano Tube FET (CNTFETs) . . . . . . . . . . . . 15 vii List of Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii 3. Memristor-CNTFET based Ternary Full Adders . . . . . . . . . . . . . . 20 3.1 Carry ripple adder . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Ternary Carry Lookahead Adder . . . . . . . . . . . . . . . . . . . 21 3.3 Carry Skip Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 27 4. Low Power Scalable Ternary Hybrid Full Adder Realization . . . . . . . 29 4.1 Proposed Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.1 Carry Circuit Generation . . . . . . . . . . . . . . . . . . . 29 4.1.2 Sum Circuit Generation . . . . . . . . . . . . . . . . . . . . 31 4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5. CNTFET Design of a Multiple-Port Ternary Register File . . . . . . . . 38 5.1 Ternary D-latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1.1 Ternary Logic Gates . . . . . . . . . . . . . . . . . . . . . . 38 5.1.2 Dynamic D-latch . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1.3 Multiplixer-based D-latch . . . . . . . . . . . . . . . . . . . 41 5.2 Master-Slave Ternary D-Flip-Flop . . . . . . . . . . . . . . . . . . . 42 5.3 Multi-Port Register File . . . . . . . . . . . . . . . . . . . . . . . . 45 5.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6. CNTFET-based Ternary Multiply-and-Accumulate Unit . . . . . . . . . 51 6.1 Ternary Arithmetic and implementations . . . . . . . . . . . . . . . 51 6.1.1 CNTFET-based Ternary Logic Gates . . . . . . . . . . . . . 51 6.1.2 Single-trit Multiplier Architecture . . . . . . . . . . . . . . . 52 6.1.3 Single Trit Full Adder . . . . . . . . . . . . . . . . . . . . . 53 6.2 Ternary Multiply-Accumulate Architecture . . . . . . . . . . . . . . 53 6.2.1 5-trit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.2.2 10-trit Full Adder . . . . . . . . . . . . . . . . . . . . . . . 55 6.2.3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2.4 MAC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2.5 Optimized MAC . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3 Simulation Results and Discussion . . . . . . . . . . . . . . . . . . 59 7. Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 61 Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 viii List of Figures Figure Page 2.1 Traditional CNTFET Architecture [1] . . . . . . . . . . . . . . . . . . 16 3.1 Two-bit half adder using memristor and CNTFET. . . . . . . . . . . 21 3.2 CNTFET and VTEAM memristor implementation of a) 4-bit carry ripple adder, b) 4-bit carry lookahead adder, and c) carry skip adder . 22 3.3 CNTFET and VTEAM memristor implementation of MTL design architecture of p and g. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.4 The simulation results of 4-bit CLA adder using CNTFET and VTEAM memristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 Block diagram of proposed SUM . . . . . . . . . . . . . . . . . . . . . 30 4.2 Proposed carry output circuit diagram . . . . . . . . . . . . . . . . . 32 4.3 XOR circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.4 Transient Analysis for (a) Cin = 0, (b) Cin = 1, (c) sneak path detection 36 4.5 Implementation of n-bit FA . . . . . . . . . . . . . . . . . . . . . . . 37 4.6 Performance of proposed FA with 0.9V supply voltage . . . . . . . . . 37 5.1 Circuit realization of the proposed designs (a) STI and (b) TNAND. . 39 5.2 Circuit realization of the proposed designs (a) Dynamic D-latch and (b) N-CNTFET only D-latch. . . . . . . . . . . . . . . . . . . . . . . 40 ix 5.3 CNTFET based ternary D flip-flop . . . . . . . . . . . . . . . . . . . 42 5.4 Proposed ternary Master-Slave D-flip-flop . . . . . . . . . . . . . . . 42 5.5 Proposed ternary DFF waveform . . . . . . . . . . . . . . . . . . . . 44 5.6 Proposed ternary dynamic and static latches waveform . . . . . . . . 45 5.7 Proposed Ternary Register . . . . . . . . . . . . . . . . . . . . . . . . 46 5.8 Proposed 8 x 32 Register File . . . . . . . . . . . . . . . . . . . . . . 47 5.9 Number of transistors and Power of the five design implementation of RF with various number of ports . . . . . . . . . . . . . . . . . . . . 50 6.1 Single-trit Multiplier implementation . . . . . . . . . . . . . . . . . . 54 6.2 Single-trit half adder implementation . . . . . . . . . . . . . . . . . . 55 6.3 Proposed 5-trit MAC architectures (a) serial approach, (b) optimized serial and (c) pipelined approach. . . . . . . . . . . . . . . . . . . . . 56 6.4 (a) Multiplication process of design-I (b) Multiplication Process of design-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
520	3		_aAbstract: Logical systems takes part in every Computing machines which is the bottom line in the modern life. They determine the design, the performance and the understanding we need to shape the computer. For decades, the logical systems had only been depending on the binary logic system. Researchers claimed that the traditional binary logic would exceed its limits and there should be other logical systems to be used. Multi-valued logic (MVL) is the future in the technology we seek to improve. Among the many options in MVL, ternary logic has been showing a huge improvements in the computing realm. It solved many problems of the binary logic in which can be concluded into the issues of interconnections, implementation complexity and more information can be stored. In this thesis, design and implementation of ternary systems using carbon nano tube FET (CNTFET). Besides, the implementation of ternary circuits such as adders using CNTFET and memristors, multipliers and sequential circuits. Unlike CMOS technology, CNTFET technology offers a huge improvements in terms of delay and power because of better conductivity of the carbon and better thermal insulation. The different designs are proposed using CNTFET and memristor technology to optimize the delay and power as possible. The comparison is held to choose the optimum design of the full adders. The simulator for memristors is VTEAM SPICE while CNTFET is Standford univeristy SPICE. xv Keywords Ternary Logic Systems, CNTFET, Digital Design, Register File, MAC
546			_aText in English, abstracts in English and Arabic
650		4	_aMSD _9317
655		7	_2NULIB _aDissertation, Academic _9187
690			_aMSD _9317
942			_2ddc _cTH
999			_c10294 _d10294