EMBEDDED LOGIC ANLYZER FOR STORAGE PROTOCOLS /
Ahmed Hassan
- 2018
- 74 p. ill. 21 cm.
Supervisor:
Thesis (M.A.)—Nile University, Egypt, 2018 .
"Includes bibliographical references"
Contents: TABLE OF CONTENTS DEDICATION................................................................................................................... 2 ACKNOWLEDGEMENTS ............................................................................................. 3 LIST OF TABLES ............................................................................................................ 6 LIST OF FIGURES .......................................................................................................... 7 Abstract .............................................................................................................................. 9 Chapter 1 Introduction................................................................................................... 11 1.1 Motivation .................................................................................................... 11 1.1 Approach outline .......................................................................................... 13 Chapter 2 Background and related work ..................................................................... 14 1.2 Background .................................................................................................. 14 2.1.1 Hardware Emulation ................................................................................. 14 2.1.2 Introduction .............................................................................................. 15 2.1.3 Emulation vs Prototyping ......................................................................... 16 2.1.4 Mentor Graphics Veloce Emulation Platform .......................................... 17 2.1.5 ICE (In-Circuit Emulation) ....................................................................... 19 2.1.6 ICE for Storage (iSolve SAS) ................................................................... 21 2.2 Related work ................................................................................................ 24 2.2.1 Xilinx ChipScope ..................................................................................... 24 2.2.2 Altera Signaltap debugger ........................................................................ 25 2.2.3 On-Chip FPGA debugger ......................................................................... 26 Chapter 3 Current iSolve Solution System ................................................................... 28 1.3 Introduction .................................................................................................. 28 3.1.1 SAS Protocol ............................................................................................ 28 3.1.1.1 SAS Layers ........................................................................................... 30 3.1.1.2 SAS Packets .......................................................................................... 33 3.1.2 iSolve SAS Speed Adapter ....................................................................... 35 3.1.3 iSolve SAS Speed Adapter In-Circuit ...................................................... 36 3.1.4 iSolve SAS Speed Adapter Architecture .................................................. 38 3.1.5 Emulation Interface .................................................................................. 40 3.1.6 iSolve SAS Speed Adapter IP .................................................................. 41 3.1.6.1 Description ............................................................................................ 41 5 Chapter 4 Proposed Embedded Logic Analyzer .......................................................... 43 1.4 System overview .......................................................................................... 44 4.1 System architecture ...................................................................................... 46 4.2 Detailed architecture .................................................................................... 47 4.3 Hardware Implementation ............................................................................ 49 4.3.1 Converter .................................................................................................. 49 4.3.2 Tracker ...................................................................................................... 50 4.3.3 FIFO.......................................................................................................... 52 4.3.4 Unload ...................................................................................................... 54 4.3.5 FIFO2SPI .................................................................................................. 56 4.3.6 GPIO ......................................................................................................... 57 1.5 Software Implementation ............................................................................. 59 1.6 Usage and Running ...................................................................................... 60 4.3.7 Post Processing Example .......................................................................... 60 4.4 Results .......................................................................................................... 64 4.4.1 FPGA utilization ....................................................................................... 64 4.4.2 Tool Usage ................................................................................................ 66 4.4.3 Conclusion ................................................................................................ 67 4.4.4 Future work............................................................................................... 69 Chapter 5 References ...................................................................................................... 70 APPENDIX A .................................................................................................................. 72 1.1 Front Panel Controls..................................................................................... 72 1.2 Rear Panel Connections ............................................................................... 74
Abstract: Serial Attached SCSI (SAS) is a high-speed, point-to-point technology initially designed to operate at speeds up to 22.5 Gb/sec. System designers have found that point-to-point serial connections are inherently more reliable than shared bandwidth parallel connections. As a result, point-to-point serial connections have become the preferred method for implementing high-availability systems. SAS based disk drives are taking advantage of this feature. This is a key requirement of high-availability server networks that call for redundant paths to all devices in the system. Increased bandwidth and performance requirements of enterprise systems, especially those involving video streaming or high levels of transactional-data, such as reservation or billing systems, have meant that SAS has become an industry standard in the storage application space. SAS storage environments usually consist of a mixture of disk drives, host bus adapters and expanders. SAS allows for addressing of over 16,000 devices. Such systems are very complex in terms of number of devices, protocol complexity and maintainability. The SAS Embedded logic Analyzer is a hardware design IP integrated with SAS designs for protocol analysis and debugging. The SAS embedded protocol analyzer address the unique characteristics of the SAS protocol as a complex standard by providing protocol traffic capturing and packets decoding. The SAS embedded logic analyzer allows debugging SAS protocol issues, and quickly identify frame communication problems by proving high-level SAS frames capturing.