Memristor And Inverse Memristor Emulators And Applications /
Haneen Gamal Mohamed
- 2020
- 114 p. ill. 21 cm.
Supervisor:Ahmed G. Radwan
Thesis (M.A.)—Nile University, Egypt, 2020 .
"Includes bibliographical references"
Contents: CHAPTER 1 : INTRODUCTION .............................................................................. 10 1.1. SCOPE ................................................................................................ 10 1.2. ORGANIZATION OF THESIS .................................................................. 10 CHAPTER 2 : LITERATURE SURVEY .................................................................. 12 2.1. MEMRISTOR MODELS ......................................................................... 13 2.1.1. Linear Ion Drift: .................................................................................... 17 2.1.1.1. The frequency response of the resistance of memristors: ......................................... 18 2.1.2. Non-linear Ion Drift Model: .................................................................. 20 2.1.3. Simmons Tunneling Model: .................................................................. 22 2.1.4. TEAM (ThrEshold Adaptive Memristor Model): ................................. 23 2.1.5. VTEAM (Voltage Threshold Assisted Model) : ................................... 23 2.2. WINDOW FUNCTIONS ......................................................................... 24 2.2.1. Joglekar: ................................................................................................ 25 2.2.1. Biolek: ................................................................................................... 25 2.2.2. Strukovet. al: ......................................................................................... 27 2.2.3. Benderliet. al: ........................................................................................ 28 2.2.4. TEAM: .................................................................................................. 29 2.2.5. Prodromakis: ......................................................................................... 30 2.3. APPLICATIONS .................................................................................... 30 2.3.1. Digital Applications .............................................................................. 30 2.3.1. Chaotic Oscillator Circuit ...................................................................... 33 2.3.2. Relaxation oscillator .............................................................................. 34 CHAPTER 3 : SYMMETRIC AND ASYMMETRIC MEMRISTOR-BASED VOLTAGE CONTROLLED RELAXATION OSCILLATOR AND APPLICATIONS .......................................................................................................... 36 3.1. INTRODUCTION ................................................................................... 36 3.2. R-M AND M-R BASED VOLTAGE-CONTROLLED OSCILLATOR .......... 37 3.2.1. Mathematical Analysis .......................................................................... 38 3.2.2. R-M Voltage Based Relaxation Oscillator: (i.e. ′ = 0 ).................... 39 3.2.2.1. Oscillation Condition ............................................................................................... 40 3.2.2.2. Oscillation Frequency .............................................................................................. 41 3.3. M -R BASED RELAXATION OSCILLATOR: (I.E. ′ = 0 ) .................... 42 3.4. INTRODUCTION ................................................................................... 54 3.5. SIMULATION RESULTS AND APPLICATIONS ........................................ 45 3.5.1. SPICE Simulations with linear HP model ............................................. 45 iii 3.6. POWER CONSUMPTION OF MEMRISTOR-BASED OSCILLATOR: ............. 47 3.7. SIMULATIONS WITH A NON-LINEAR EXPONENTIAL MODEL ................. 47 3.8. APPLICATION: FREQUENCY MODULATOR .......................................... 51 3.9. VOLTAGE-CONTROLLED ASYMMETRIC OSCILLATOR ......................... 52 CHAPTER 4 : INVERSE MEMRISTOR AND ITS EMULATORS ...................... 54 4.1. INVERSE MEMRISTOR MODEL ............................................................. 55 4.2. MODEL OF SERIES AND PARALLEL CONNECTED NETWORKS WITH MEMRISTOR AND INVERSE MEMRISTOR ........................................................................ 56 4.3. CIRCUIT IDENTIFICATION AND NUMERICAL SIMULATIONS ................. 57 4.3.1. Impedance Analysis .............................................................................. 59 4.4. DIFFERENT NETWORK COMBINATIONS OF MEMRISTIVE ELEMENTS FROM THE GENERAL EQUATION. ................................................................................... 61 4.5. INVERSE MEMRISTOR EMULATOR ....................................................... 73 4.5.1. Current-Controlled Inverse Memristor Emulator based Multiplier ....... 73 4.5.2. Inverse Memristor Emulator Based Threshold ..................................... 76 4.5.3. Combined Memristor- Inverse Memristor Emulator Based BJT Transistor 78 4.5.4. Experimental Result .............................................................................. 79 4.5.5. Discussion and Comparison .................................................................. 82 4.6. INVERSE MEMCAPACITOR AND MEMINDUCTOR .................................. 82 4.6.1. Inverse meminductor ............................................................................. 82 4.6.1.1. Inverse meminductor mathematical model .............................................................. 82 4.6.1.2. Circuit realization of Inverse meminductor model ................................................... 86 CHAPTER 5 : ANALOG PWL MEMRISTOR EMULATOR ............................... 88 5.1. INTRODUCTION ................................................................................... 88 5.2. PROPOSED PWLM SWITCHING MODEL MEMRISTOR ......................... 89 5.2.1. Two-Level PWL Switching Memristor Model ..................................... 89 5.2.2. Multi-Level PWL Switching Memristor Model .................................... 91 5.3. LOOP FILTER OF PHASE-LOCKED LOOP (APPLICATION) ..................... 96 CHAPTER 6 : DISCUSSION AND CONCLUSIONS .............................................. 98 REFERENCES ...........................................................................................................
Abstract: Memristor based oscillators are an essential subject of non-linear circuit theory in which relaxation oscillators can be constructed without reactive components. A family of voltage-controlled relaxation oscillators based on memristor is summed up in this thesis. The function of memristor dependent voltage control oscillator circuits is proved with mathematical modeling and circuit analysis. For the frequency and conditions of characteristic oscillation, expressions are obtained in multiple situations where a closed-form for each case is added. The effect on the frequency and conditions of the swing of circuit parameters is numerically evaluated. However, multiple transient SPICE simulations are used to test the resulting equations. With numerically analysis and SPICE simulations, the power output of each oscillator is accomplished and verified. Besides, a memristive oscillator control with a voltage allows for additional freedom in the design, which improves design versatility. To show the oscillation principle concept, the nonlinear exponential memristor model is used and tested well. For this procedure, the reference voltage influence on the output voltage is expanded using two instances of the voltage-controlled memory-based stimulation oscillator (VCO). This VCO has a small size (nanoscale) and is more compact relative to the standard storage devices. Also, three different inverse memristor emulators based on several active blocks are presented. One of the proposed emulators is realized by a second-generation current conveyor (CCII) and analog voltage multiplier with passive elements. The other two introduced emulators are designed using the current feedback operational amplifier (CFOA) with two switches or two BJT transistors. One of the proposed emulators has the advantage that it switches between the inverse memristor and memristor at the same time but in different frequencies with a smaller number of components. The introduced circuitry is simulated to validate the concept of inverse memristor showing the pinched hysteresis loop in the I-V plane. One selected emulator is verified experimentally. A comparison of the three proposed emulators is presented to highlight the number of active, passive components, and the range of frequency. Finally, an analog PWL memristor model is presented with different levels that can be implemented on an FPGA in future work and show that such an implementation can be used to generate chaos, as an example. So necessarily, it has been emulated memristor behavior using programmable transistor circuits. Then will be used this implementation as a module to mimic chaotic generators later. By using FPGAs and implementing chaotic generators will be something that has not come across before.