Beerel, Peter A. <br/><br/>
A designer’s guide to asynchronous VLSI /  
Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti. 
 - Cambridge ;    New York :    Cambridge University Press,    2010. 
 - xii, 339 p. :    ill. ;    26 cm. 
<br/><br/>Includes bibliographical references and index. 
<br/><br/>Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith. 
<br/><br/> This book provides an introduction to this diverse area of VLSI from a designer’s point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future. 
<br/><br/><label>ISBN: </label>9780521872447 
<br/><br/><label>LCCN: </label>2009042290 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits -- Very large scale integration -- Computer-aided design.<br/>Integrated circuits -- Very large scale integration -- Design and construction.
<br/><br/><label>Dewey Class. No.: </label>621.395