Wile, Bruce. <br/><br/>
Comprehensive functional verification the complete industry cycle /  
Bruce Wile, John C. Goss, Wolfgang Roesner. 
 - Amsterdam ;    Boston :    Elsevier/Morgan Kaufmann,    c2005. 
 - xxiii, 676 p. :    ill. ;    24 cm. 
<br/><br/>Includes bibliographical references (p. 657-662) and index. 
<br/><br/>Verification in the Chip Design Process -- Verification Flow -- Fundamentals of Simulation Based Verification -- The Verification Plan -- HDLs and Simulation Engines -- Creating Environments -- Strategies for Simulation based Stimulus Generation -- Strategies for Results Checking in Simulation Based Verification -- System Reset and Bring-up -- Re-Use Strategies and System Simulation -- Completing the Verification Cycle -- Advanced Verification Techniques. 
<br/><br/><label>ISBN: </label>0127518037 
<br/><br/><label>LCCN: </label>2005299338 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Integrated circuits -- Verification.<br/>Computer engineering.
<br/><br/><label>Dewey Class. No.: </label>621.381548