Amr Ali Mahmoud Mohammaden <br/><br/>
Design and implementation of ternary systems using CNTFET 
/Amr Ali Mahmoud Mohammaden 
 -  2024 
 - 83 p.   ill.   21 cm.  
<br/><br/>Supervisor: Ahmed Gomaa Radwan 
<br/><br/>Thesis (MS.c)—Nile University, Egypt, 2024.<br/> 
<br/><br/>"Includes bibliographical references" 
<br/><br/>Contents: Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv<br/>List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix<br/>List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi<br/>Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv<br/>Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv<br/>Chapters:<br/>1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1<br/>1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1<br/>1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2<br/>1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . 4<br/>2. Literature Survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5<br/>2.1 MVL Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5<br/>2.1.1 Ternary Number Representations . . . . . . . . . . . . . . . 6<br/>2.1.2 Signed and Unsigned Representation . . . . . . . . . . . . . 7<br/>2.1.3 Ternary Arithmetic Operations . . . . . . . . . . . . . . . . 10<br/>2.1.4 Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . 12<br/>2.1.5 Logic Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . 13<br/>2.1.6 Carbon Nano Tube FET (CNTFETs) . . . . . . . . . . . . 15<br/>vii<br/>List of Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii<br/>3. Memristor-CNTFET based Ternary Full Adders . . . . . . . . . . . . . . 20<br/>3.1 Carry ripple adder . . . . . . . . . . . . . . . . . . . . . . . . . . . 20<br/>3.2 Ternary Carry Lookahead Adder . . . . . . . . . . . . . . . . . . . 21<br/>3.3 Carry Skip Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25<br/>3.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 27<br/>4. Low Power Scalable Ternary Hybrid Full Adder Realization . . . . . . . 29<br/>4.1 Proposed Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29<br/>4.1.1 Carry Circuit Generation . . . . . . . . . . . . . . . . . . . 29<br/>4.1.2 Sum Circuit Generation . . . . . . . . . . . . . . . . . . . . 31<br/>4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 33<br/>5. CNTFET Design of a Multiple-Port Ternary Register File . . . . . . . . 38<br/>5.1 Ternary D-latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38<br/>5.1.1 Ternary Logic Gates . . . . . . . . . . . . . . . . . . . . . . 38<br/>5.1.2 Dynamic D-latch . . . . . . . . . . . . . . . . . . . . . . . . 40<br/>5.1.3 Multiplixer-based D-latch . . . . . . . . . . . . . . . . . . . 41<br/>5.2 Master-Slave Ternary D-Flip-Flop . . . . . . . . . . . . . . . . . . . 42<br/>5.3 Multi-Port Register File . . . . . . . . . . . . . . . . . . . . . . . . 45<br/>5.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 47<br/>6. CNTFET-based Ternary Multiply-and-Accumulate Unit . . . . . . . . . 51<br/>6.1 Ternary Arithmetic and implementations . . . . . . . . . . . . . . . 51<br/>6.1.1 CNTFET-based Ternary Logic Gates . . . . . . . . . . . . . 51<br/>6.1.2 Single-trit Multiplier Architecture . . . . . . . . . . . . . . . 52<br/>6.1.3 Single Trit Full Adder . . . . . . . . . . . . . . . . . . . . . 53<br/>6.2 Ternary Multiply-Accumulate Architecture . . . . . . . . . . . . . . 53<br/>6.2.1 5-trit Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . 54<br/>6.2.2 10-trit Full Adder . . . . . . . . . . . . . . . . . . . . . . . 55<br/>6.2.3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59<br/>6.2.4 MAC Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 59<br/>6.2.5 Optimized MAC . . . . . . . . . . . . . . . . . . . . . . . . 59<br/>6.3 Simulation Results and Discussion . . . . . . . . . . . . . . . . . . 59<br/>7. Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . . . . . 61<br/>Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2<br/>viii<br/>List of Figures<br/>Figure Page<br/>2.1 Traditional CNTFET Architecture [1] . . . . . . . . . . . . . . . . . . 16<br/>3.1 Two-bit half adder using memristor and CNTFET. . . . . . . . . . . 21<br/>3.2 CNTFET and VTEAM memristor implementation of a) 4-bit carry<br/>ripple adder, b) 4-bit carry lookahead adder, and c) carry skip adder . 22<br/>3.3 CNTFET and VTEAM memristor implementation of MTL design architecture of p and g. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23<br/>3.4 The simulation results of 4-bit CLA adder using CNTFET and VTEAM<br/>memristor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28<br/>4.1 Block diagram of proposed SUM . . . . . . . . . . . . . . . . . . . . . 30<br/>4.2 Proposed carry output circuit diagram . . . . . . . . . . . . . . . . . 32<br/>4.3 XOR circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 34<br/>4.4 Transient Analysis for (a) Cin = 0, (b) Cin = 1, (c) sneak path detection 36<br/>4.5 Implementation of n-bit FA . . . . . . . . . . . . . . . . . . . . . . . 37<br/>4.6 Performance of proposed FA with 0.9V supply voltage . . . . . . . . . 37<br/>5.1 Circuit realization of the proposed designs (a) STI and (b) TNAND. . 39<br/>5.2 Circuit realization of the proposed designs (a) Dynamic D-latch and<br/>(b) N-CNTFET only D-latch. . . . . . . . . . . . . . . . . . . . . . . 40<br/>ix<br/>5.3 CNTFET based ternary D flip-flop . . . . . . . . . . . . . . . . . . . 42<br/>5.4 Proposed ternary Master-Slave D-flip-flop . . . . . . . . . . . . . . . 42<br/>5.5 Proposed ternary DFF waveform . . . . . . . . . . . . . . . . . . . . 44<br/>5.6 Proposed ternary dynamic and static latches waveform . . . . . . . . 45<br/>5.7 Proposed Ternary Register . . . . . . . . . . . . . . . . . . . . . . . . 46<br/>5.8 Proposed 8 x 32 Register File . . . . . . . . . . . . . . . . . . . . . . 47<br/>5.9 Number of transistors and Power of the five design implementation of<br/>RF with various number of ports . . . . . . . . . . . . . . . . . . . . 50<br/>6.1 Single-trit Multiplier implementation . . . . . . . . . . . . . . . . . . 54<br/>6.2 Single-trit half adder implementation . . . . . . . . . . . . . . . . . . 55<br/>6.3 Proposed 5-trit MAC architectures (a) serial approach, (b) optimized<br/>serial and (c) pipelined approach. . . . . . . . . . . . . . . . . . . . . 56<br/>6.4 (a) Multiplication process of design-I (b) Multiplication Process of<br/>design-II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 
<br/><br/> Abstract: Logical systems takes part in every Computing machines which is the bottom<br/>line in the modern life. They determine the design, the performance and the understanding we need to shape the computer. For decades, the logical systems had<br/>only been depending on the binary logic system. Researchers claimed that the traditional binary logic would exceed its limits and there should be other logical systems<br/>to be used. Multi-valued logic (MVL) is the future in the technology we seek to<br/>improve. Among the many options in MVL, ternary logic has been showing a huge<br/>improvements in the computing realm. It solved many problems of the binary logic in<br/>which can be concluded into the issues of interconnections, implementation complexity and more information can be stored. In this thesis, design and implementation<br/>of ternary systems using carbon nano tube FET (CNTFET). Besides, the implementation of ternary circuits such as adders using CNTFET and memristors, multipliers<br/>and sequential circuits. Unlike CMOS technology, CNTFET technology offers a huge<br/>improvements in terms of delay and power because of better conductivity of the carbon and better thermal insulation. The different designs are proposed using CNTFET<br/>and memristor technology to optimize the delay and power as possible. The comparison is held to choose the optimum design of the full adders. The simulator for<br/>memristors is VTEAM SPICE while CNTFET is Standford univeristy SPICE.<br/>xv<br/>Keywords<br/>Ternary Logic Systems, CNTFET, Digital Design, Register File, MAC<br/> 
<br/><br/><br/>Text in English, abstracts in English and Arabic 
<br/><br/><label>Standard No.: </label>0009-0009-2269-0800  ORCID 
<br/><br/><label>Subjects--Topical Terms: </label><br/>MSD
<br/><br/><label>Index Terms--Genre/Form: </label><br/>Dissertation, Academic
<br/><br/><label>Dewey Class. No.: </label>621