Time to Digital Converter Phase Locked Loop for Microprocessor Clock Generation / Mamdouh Osama Mahmoud Mohamed Abdelmejeed

Supervisor: Rafik Guindi

Thesis (M.A.)—Nile University, Egypt, 2014 .

"Includes bibliographical references"

Contents:
Chapter1: Introduction ............................................................................................................... 1
1.1 Motivation .................................................................................................................... 1
1.2 Thesis Organization ...................................................................................................... 3
Chapter 2: PLLs Literature Review ........................................................................................ 4
2.1 PLL Applications .......................................................................................................... 4
2.1.1 Clock generation in microprocessors .................................................................... 4
2.1.2 Spread spectrum .................................................................................................... 5
2.1.3 Frequency synthesis .............................................................................................. 6
2.1.4 Clock and data recovery ........................................................................................ 6
2.2 PLLs principle of operation .......................................................................................... 7
2.3 Types of PLLs .............................................................................................................. 8
2.3.1 Analog PLLs ......................................................................................................... 8
VII
2.3.2 All digital PLLs ................................................................................................... 13
2.4 PLLs Frequency Domain Analysis ............................................................................. 17
2.5 PLL Design Parameters .............................................................................................. 18
2.6 Other PLL Types ........................................................................................................ 20
Chapter 3: Time to Digital Converters .................................................................................. 22
3.1 TDCs Overview .......................................................................................................... 22
3.1.1 Non-idealities in TDC characteristics ................................................................. 24
3.1.2 TDC figures of merit ........................................................................................... 26
3.2 TDCs Literature Review ............................................................................................. 26
3.2.1 Analog TDCs....................................................................................................... 26
3.2.2 Counter based TDC ............................................................................................. 27
3.2.3 Delay-line based TDC ......................................................................................... 28
3.2.4 Vernier delay-line based TDC............................................................................. 30
3.2.5 Noise shaping TDC ............................................................................................. 32
3.2.6 Time sampling TDC ............................................................................................ 34
3.2.7 Two-stage based TDC ......................................................................................... 36
Chapter 4: Proposed Novel TDC Architecture ..................................................................... 39
4.1 Tradeoffs between Different TDC Topologies ........................................................... 39
4.1.1 Convergence range vs. area and throughput ....................................................... 39
VIII
4.1.2 Resolution vs. throughput ................................................................................... 39
4.2 System Level Implementation .................................................................................... 41
4.2.1 First TDC technique [33] .................................................................................... 41
4.2.2 Second TDC technique [34] ................................................................................ 44
4.3 System blocks Implementation. .................................................................................. 47
4.3.1 Synchronizer design ............................................................................................ 47
4.3.2 Oscillator design .................................................................................................. 51
4.3.3 Coarse and fine counters ..................................................................................... 51
4.3.4 Time amplifier ..................................................................................................... 52
4.3.5 Delay control module .......................................................................................... 54
4.3.6 Asynchronous control block................................................................................ 55
4.4 Simulation Results ...................................................................................................... 56
Chapter 5: PLL Implementation ........................................................................................... 61
5.1 System Block Diagram ............................................................................................... 62
5.1.1 Frequency lock loop ............................................................................................ 63
5.1.2 Phase/Frequency lock loop.................................................................................. 64
5.2 PLL Design Methodology .......................................................................................... 66
5.3 System Blocks Implementation .................................................................................. 72
5.3.1 Sigma-Delta modulator ....................................................................................... 72
IX
5.3.2 Phase frequency detector ..................................................................................... 74
5.3.3 Digital loop filter ................................................................................................. 75
5.3.4 Loop divider ........................................................................................................ 75
5.3.5 DCO .................................................................................................................... 76
5.3.6 Layout for the digital blocks ............................................................................... 79
5.4 Closed Loop Simulation Results ................................................................................ 80
5.4.1 Lock Time ........................................................................................................... 80
5.4.2 Jitter ..................................................................................................................... 81
Chapter 6: Conclusion ........................................................................................................... 87
6.1 Future work................................................................................................................. 88
6.1.1 TDC design ......................................................................................................... 88
6.1.2 PLL design .......................................................................................................... 88
References ...............................................................................................................................

Abstract:
The evolution of the CMOS process is continuously heading towards improving the performance of digital integrated circuits. To achieve high performance (speed) while keeping the area and power consumption as small as possible, the minimum channel length and the supply voltage steadily decrease with newer CMOS processes. However, the performance of analog integrated circuits doesn’t necessarily improve with newer CMOS technology. In fact, as the supply voltage scales down with the migration to lower process nodes, the available signal range shrinks. As the signal level decreases a lower noise level is required to maintain the same Signal to Noise Ratio (SNR) and the same dynamic range. Also, the overdrive voltage of the transistors does not scale with technology, making it very hard to implement analog circuits with a stack of more than 3 transistors like the telescopic cascode amplifier. As a result, circuit designers have been trying to find digital alternatives for analog circuit. The Phase Locked Loop (PLL) is a famous example. In this thesis, a Time to Digital Converter (TDC) All-Digital Phase Locked Loop (ADPLL) is designed to replace analog PLLs in microprocessor clock generation.
First, a new technique for TDC design is proposed. The proposed technique is a 2-stage TDC which uses an oscillator-based TDC for conversion. The time residue from the first stage is generated directly after the stop signal is asserted and saved in the form of a phase-shift between two oscillating signals. Instead of using two stages, an asynchronous control block is implemented to reuse the same hardware block for both the first and second conversion stages. This technique not only reduces power and area, but also eliminates the TDC nonlinearity due to the mismatch between the two stages. A throughput of 400 MS/s for a 10-bit resolution, a time resolution of 2.6 ps, a DNL of 0.38, and an INL of 0.402 are achieved.
XVII
This TDC was used in the implementation of an ADPLL. Simulation results for the PLL proves that the proposed system combines the advantages of analog PLLs like low jitter and high linearity with the advantages of digital circuits like scalability, small area, and low power consumption . The Proposed PLL has a range of 1.4 GHz – 4.4 GHz, maximum lock time of 0.6 us, maximum RMS jitter of 0.8 ps, and a total power consumption of 12.5 mW at 3 GHz lock frequency.

Text in English, abstracts in English.