EMBEDDED LOGIC ANLYZER FOR STORAGE PROTOCOLS / (Record no. 9067)

MARC details
000 -LEADER
fixed length control field 08592nam a22002537a 4500
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 210830s2018 ||||f mb|| 00| 0 eng d
040 ## - CATALOGING SOURCE
Original cataloging agency EG-CaNU
Transcribing agency EG-CaNU
041 0# - Language Code
Language code of text eng
Language code of abstract eng
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 627
100 0# - MAIN ENTRY--PERSONAL NAME
Personal name Ahmed Hassan
245 1# - TITLE STATEMENT
Title EMBEDDED LOGIC ANLYZER FOR STORAGE PROTOCOLS /
Statement of responsibility, etc. Ahmed Hassan
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Date of publication, distribution, etc. 2018
300 ## - PHYSICAL DESCRIPTION
Extent 74 p.
Other physical details ill.
Dimensions 21 cm.
500 ## - GENERAL NOTE
Materials specified Supervisor:
502 ## - Dissertation Note
Dissertation type Thesis (M.A.)—Nile University, Egypt, 2018 .
504 ## - Bibliography
Bibliography "Includes bibliographical references"
505 0# - Contents
Formatted contents note Contents:<br/>TABLE OF CONTENTS<br/>DEDICATION................................................................................................................... 2<br/>ACKNOWLEDGEMENTS ............................................................................................. 3<br/>LIST OF TABLES ............................................................................................................ 6<br/>LIST OF FIGURES .......................................................................................................... 7<br/>Abstract .............................................................................................................................. 9<br/>Chapter 1 Introduction................................................................................................... 11<br/>1.1 Motivation .................................................................................................... 11<br/>1.1 Approach outline .......................................................................................... 13<br/>Chapter 2 Background and related work ..................................................................... 14<br/>1.2 Background .................................................................................................. 14<br/>2.1.1 Hardware Emulation ................................................................................. 14<br/>2.1.2 Introduction .............................................................................................. 15<br/>2.1.3 Emulation vs Prototyping ......................................................................... 16<br/>2.1.4 Mentor Graphics Veloce Emulation Platform .......................................... 17<br/>2.1.5 ICE (In-Circuit Emulation) ....................................................................... 19<br/>2.1.6 ICE for Storage (iSolve SAS) ................................................................... 21<br/>2.2 Related work ................................................................................................ 24<br/>2.2.1 Xilinx ChipScope ..................................................................................... 24<br/>2.2.2 Altera Signaltap debugger ........................................................................ 25<br/>2.2.3 On-Chip FPGA debugger ......................................................................... 26<br/>Chapter 3 Current iSolve Solution System ................................................................... 28<br/>1.3 Introduction .................................................................................................. 28<br/>3.1.1 SAS Protocol ............................................................................................ 28<br/>3.1.1.1 SAS Layers ........................................................................................... 30<br/>3.1.1.2 SAS Packets .......................................................................................... 33<br/>3.1.2 iSolve SAS Speed Adapter ....................................................................... 35<br/>3.1.3 iSolve SAS Speed Adapter In-Circuit ...................................................... 36<br/>3.1.4 iSolve SAS Speed Adapter Architecture .................................................. 38<br/>3.1.5 Emulation Interface .................................................................................. 40<br/>3.1.6 iSolve SAS Speed Adapter IP .................................................................. 41<br/>3.1.6.1 Description ............................................................................................ 41<br/>5<br/>Chapter 4 Proposed Embedded Logic Analyzer .......................................................... 43<br/>1.4 System overview .......................................................................................... 44<br/>4.1 System architecture ...................................................................................... 46<br/>4.2 Detailed architecture .................................................................................... 47<br/>4.3 Hardware Implementation ............................................................................ 49<br/>4.3.1 Converter .................................................................................................. 49<br/>4.3.2 Tracker ...................................................................................................... 50<br/>4.3.3 FIFO.......................................................................................................... 52<br/>4.3.4 Unload ...................................................................................................... 54<br/>4.3.5 FIFO2SPI .................................................................................................. 56<br/>4.3.6 GPIO ......................................................................................................... 57<br/>1.5 Software Implementation ............................................................................. 59<br/>1.6 Usage and Running ...................................................................................... 60<br/>4.3.7 Post Processing Example .......................................................................... 60<br/>4.4 Results .......................................................................................................... 64<br/>4.4.1 FPGA utilization ....................................................................................... 64<br/>4.4.2 Tool Usage ................................................................................................ 66<br/>4.4.3 Conclusion ................................................................................................ 67<br/>4.4.4 Future work............................................................................................... 69<br/>Chapter 5 References ...................................................................................................... 70<br/>APPENDIX A .................................................................................................................. 72<br/>1.1 Front Panel Controls..................................................................................... 72<br/>1.2 Rear Panel Connections ............................................................................... 74
520 3# - Abstract
Abstract Abstract:<br/>Serial Attached SCSI (SAS) is a high-speed, point-to-point technology initially designed to operate at speeds up to 22.5 Gb/sec. System designers have found that point-to-point serial connections are inherently more reliable than shared bandwidth parallel connections. As a result, point-to-point serial connections have become the preferred method for implementing high-availability systems. SAS based disk drives are taking advantage of this feature. This is a key requirement of high-availability server networks that call for redundant paths to all devices in the system.<br/>Increased bandwidth and performance requirements of enterprise systems, especially those involving video streaming or high levels of transactional-data, such as reservation or billing systems, have meant that SAS has become an industry standard in the storage application space. SAS storage environments usually consist of a mixture of disk drives, host bus adapters and expanders. SAS allows for addressing of over 16,000 devices. Such systems are very complex in terms of number of devices, protocol complexity and maintainability.<br/>The SAS Embedded logic Analyzer is a hardware design IP integrated with SAS designs for protocol analysis and debugging. The SAS embedded protocol analyzer address the unique characteristics of the SAS protocol as a complex standard by providing protocol traffic<br/>capturing and packets decoding. The SAS embedded logic analyzer allows debugging SAS protocol issues, and quickly identify frame communication problems by proving high-level SAS frames capturing.
546 ## - Language Note
Language Note Text in English, abstracts in English.
650 #4 - Subject
Subject Software Engineering
655 #7 - Index Term-Genre/Form
Source of term NULIB
focus term Dissertation, Academic
690 ## - Subject
School Software Engineering
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Thesis
650 #4 - Subject
-- 211
655 #7 - Index Term-Genre/Form
-- 187
690 ## - Subject
-- 211
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Date acquired Total Checkouts Full call number Date last seen Price effective from Koha item type
    Dewey Decimal Classification     Main library Main library 08/30/2021   627/ A.H.E 2018 08/30/2021 08/30/2021 Thesis