MARC details
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
120710s2010 nyua b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2010022678 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780071635196 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
007163519X |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(Sirsi) u8351 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
EG-CaNU |
| Transcribing agency |
EG-CaNU |
| Modifying agency |
EG-CaNU |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
ncode |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Kundu, Sandip. |
| 9 (RLIN) |
15394 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Nanoscale CMOS VLSI circuits : |
| Remainder of title |
design for manufacturability / |
| Statement of responsibility, etc. |
Sandip Kundu, Aswin Sreedhar. |
| 246 14 - VARYING FORM OF TITLE |
|---|
| Title proper/short title |
Nanoscale complementary metal oxide semiconductor very large-scale integration circuits |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
New York : |
| Name of publisher, distributor, etc. |
McGraw-Hill, |
| Date of publication, distribution, etc. |
c2010. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xv, 296 p. : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Semiconductor manufacturing -- Process and device variability : analysis and modeling -- Manufacturing-aware physical design closure -- Metrology, manufacturing defects, and defect extraction -- Defect impact modeling and yield improvement techniques -- Physical design and reliability -- Design for manufacturability : tools and methodologies. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
This detailed guide offers proven methods for optimizing circuit designs to increase the yield, reliability, and manufacturability of products and mitigate defects and failure. Covering the latest devices, technologies, and processes, Nanoscale CMOS VLSI Circuits: Design for Manufacturability focuses on delivering higher performance and lower power consumption. Costs, constraints, and computational efficiencies are also discussed in the practical resource. |
| 596 ## - |
|---|
| -- |
1 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Metal oxide semiconductors, Complementary |
| General subdivision |
Design and construction. |
| 9 (RLIN) |
15395 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits |
| General subdivision |
Very large scale integration |
| -- |
Design and construction. |
| 9 (RLIN) |
15396 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Nanoelectronics. |
| 9 (RLIN) |
1939 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Sreedhar, Aswin. |
| 9 (RLIN) |
15397 |