MARC details
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
120603s2010 njua b 001 0 eng |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
2009034771 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9780137045792 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0137045794 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(Sirsi) u8220 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
EG-CaNU |
| Transcribing agency |
EG-CaNU |
| Modifying agency |
EG-CaNU |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
ncode |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.39028553 |
| Edition number |
22 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Zwoliński, Mark. |
| 9 (RLIN) |
15051 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Digital system design with SystemVerilog / |
| Statement of responsibility, etc. |
Mark Zwolinski. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Upper Saddle River, N.J. : |
| Name of publisher, distributor, etc. |
Prentice Hall ; |
| Place of publication, distribution, etc. |
London : |
| Name of publisher, distributor, etc. |
Pearson Education [distributor], |
| Date of publication, distribution, etc. |
2010. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxix, 367 p. : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc. note |
Includes bibliographical references and index. |
| 505 0# - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Chapter 1: Introduction -- Chapter 2: Combinational Logic Design -- Chapter 3: Combinational Logic Using SystemVerilog Gate Models -- Chapter 4: Combinational Building Blocks -- Chapter 5: SystemVerilog Models of Sequential Logic Blocks -- Chapter 6: Synchronous Sequential Design -- Chapter 7: Complex Sequential Systems -- Chapter 8: Writing Testbenches -- Chapter 9: SystemVerilog Simulation -- Chapter 10: SystemVerilog Synthesis -- Chapter 11: Testing Digital Systems -- Chapter 12: Design for Testability -- Chapter 13: Asynchronous Sequential Design -- Chapter 14: Interfacing with the AnalogWorld. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)—and today’s most powerful, useful HDL is SystemVerilog, now an IEEE standard. Digital System Design with SystemVerilog is the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it. Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog—from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org. |
| 596 ## - |
|---|
| -- |
1 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Verilog (Computer hardware description language) |
| 9 (RLIN) |
3111 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronic digital computers |
| General subdivision |
Design and construction. |
| 9 (RLIN) |
15052 |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Computer simulation. |
| 9 (RLIN) |
15053 |