A designer’s guide to asynchronous VLSI / (Record no. 7110)

MARC details
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 120528s2010 enka b 001 0 eng
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
LC control number 2009042290
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780521872447
035 ## - SYSTEM CONTROL NUMBER
System control number (Sirsi) u8210
040 ## - CATALOGING SOURCE
Original cataloging agency EG-CaNU
Transcribing agency EG-CaNU
Modifying agency EG-CaNU
042 ## - AUTHENTICATION CODE
Authentication code ncode
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Edition number 22
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Beerel, Peter A.
9 (RLIN) 15018
245 12 - TITLE STATEMENT
Title A designer’s guide to asynchronous VLSI /
Statement of responsibility, etc. Peter A. Beerel, Recep O. Ozdag, Marcos Ferretti.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Cambridge ;
-- New York :
Name of publisher, distributor, etc. Cambridge University Press,
Date of publication, distribution, etc. 2010.
300 ## - PHYSICAL DESCRIPTION
Extent xii, 339 p. :
Other physical details ill. ;
Dimensions 26 cm.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Includes bibliographical references and index.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note Introduction -- Channel-based asynchronous design -- Modeling channel-based designs -- Pipeline performance -- Performance analysis and optimization -- Deadlock -- A taxonomy of design styles -- Synthesis-based controller design -- Micropipeline design -- Syntax-directed translation -- Quasi-delay-intensitive pipeline templates -- Timed pipeline templates -- Single-track pipeline templates -- Asynchronous crossbar -- Design example : the Fano algorith.
520 ## - SUMMARY, ETC.
Summary, etc. This book provides an introduction to this diverse area of VLSI from a designer’s point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future.
596 ## -
-- 1
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Integrated circuits
General subdivision Very large scale integration
-- Computer-aided design.
9 (RLIN) 15019
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Integrated circuits
General subdivision Very large scale integration
-- Design and construction.
9 (RLIN) 15020
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Ozdag, Recep O.
9 (RLIN) 15021
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Ferretti, Marcos.
9 (RLIN) 15022
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Source of acquisition Total Checkouts Full call number Barcode Date last seen Copy number Price effective from Koha item type
    Dewey Decimal Classification     Main library Main library General Stacks 01/26/2020 PURCHASE   621.395 / BE.D 2010 011821 11/24/2019 1 11/24/2019 Books