Modern processor design : (Record no. 6686)

MARC details
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 101020s2003 maua 000 0 eng
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0071230076
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9780071230070
035 ## - SYSTEM CONTROL NUMBER
System control number (Sirsi) u7723
040 ## - CATALOGING SOURCE
Original cataloging agency EG-CaNU
Transcribing agency EG-CaNU
Modifying agency EG-CaNU
042 ## - AUTHENTICATION CODE
Authentication code ncode
082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.3916
Edition number 22
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Shen, John Paul.
9 (RLIN) 11134
245 10 - TITLE STATEMENT
Title Modern processor design :
Remainder of title fundamentals of superscalar processors /
Statement of responsibility, etc. John Paul Shen, Mikko H. Lipasti.
250 ## - EDITION STATEMENT
Edition statement Beta ed.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. Boston ;
-- London :
Name of publisher, distributor, etc. McGraw-Hill Higher Education,
Date of publication, distribution, etc. c2005.
300 ## - PHYSICAL DESCRIPTION
Extent xiv, 642 p. :
Other physical details ill. ;
Dimensions 25 cm.
505 0# - FORMATTED CONTENTS NOTE
Formatted contents note 1 Processor Design -- 2 Pipelined Processors -- 3 Memory and I/O Systems -- 4 Superscalar Organization -- 5 Superscalar Techniques -- 6 The PowerPC 620 -- 7 Intel's P6 Microarchitecture -- 8 Survey of Superscalar Processors -- 9 Advanced Instruction Flow Techniques -- 10 Advanced Register Data Flow Techniques -- 11 Executing Multiple Threads.
520 ## - SUMMARY, ETC.
Summary, etc. dern Processor Design: Fundamentals of Superscalar Processors is an exciting new first edition from John Shen of Carnegie Mellon University & Intel and Mikko Lipasti of the University of Wisconsin--Madison. This book brings together the numerous microarchitectural techniques for harvesting more instruction-level parallelism (ILP) to achieve better processor performance that have been proposed and implemented in real machines. Other advanced techniques from recent research efforts that extend beyond ILP to exploit thread-level parallelism (TLP) are also compiled in this book. All of these techniques, as well as the foundational principles behind them, are organized and presented within a clear framework that allows for ease of comprehension. This text is intended for an advanced computer architecture course or a course in superscalar processor design. It is written at a level appropriate for senior or first year graduate level students, and can be used by professionals as well.
598 ## -
-- APPSCIE, NBK
596 ## -
-- 1
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Microprocessors
General subdivision Design and construction.
9 (RLIN) 13866
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Lipasti, Mikko H.
9 (RLIN) 13867
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Source of acquisition Total Checkouts Full call number Barcode Date last seen Copy number Price effective from Koha item type
    Dewey Decimal Classification     Main library Main library General Stacks 01/26/2020 BAC_P   621.3916 / SH.M 2003 011108 11/24/2019 1 11/24/2019 Books
    Dewey Decimal Classification     Main library Main library General Stacks 01/26/2020 BAC_P   621.3916 / SH.M 2003 011106 11/24/2019 2 11/24/2019 Books
    Dewey Decimal Classification     Main library Main library General Stacks 01/26/2020 BAC_P   621.3916 / SH.M 2003 011107 11/24/2019 3 11/24/2019 Books
    Dewey Decimal Classification     Main library Main library General Stacks 01/26/2020 BAC_P   621.3916 / SH.M 2003 011109 11/24/2019 4 11/24/2019 Books