Fundamentals of digital logic with VHDL design / (Record no. 651)

MARC details
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 090520s2009 nyua b 001 0 eng
010 ## - LIBRARY OF CONGRESS CONTROL NUMBER
LC control number 2008001634
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 0071284281
035 ## - SYSTEM CONTROL NUMBER
System control number (Sirsi) u1592
040 ## - CATALOGING SOURCE
Original cataloging agency EG-CaNU
Transcribing agency EG-CaNU
Modifying agency EG-CaNU
042 ## - AUTHENTICATION CODE
Authentication code ncode
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Edition number 22
100 1# - MAIN ENTRY--PERSONAL NAME
Personal name Brown, Stephen D.
9 (RLIN) 1410
245 10 - TITLE STATEMENT
Title Fundamentals of digital logic with VHDL design /
Statement of responsibility, etc. Stephen Brown and Zvonko Vranesic.
250 ## - EDITION STATEMENT
Edition statement 3rd ed.
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. New York, NY :
Name of publisher, distributor, etc. McGraw-Hill,
Date of publication, distribution, etc. c2009.
300 ## - PHYSICAL DESCRIPTION
Extent xx, 939 p. :
Other physical details ill. (some col.) ;
Dimensions 24 cm. +
Accompanying material 1 CD-ROM (4 3/4 in.)
440 ## - SERIES STATEMENT/ADDED ENTRY--TITLE
Title McGraw-Hill series in electrical and computer engineering
9 (RLIN) 164
500 ## - GENERAL NOTE
General note Accompanying CD-ROM contains Altera's Quartus II CAD system and all VHDL examples presented in the book.
500 ## - GENERAL NOTE
General note Accompanying CD-ROM contains Altera's Quartus II CAD system and all VHDL examples presented in the book.
538 ## - SYSTEM DETAILS NOTE
System details note Minimum system requirements (PC): Pentium III processor or later; Windows XP or later; USB port for connecting a USB-Blaster; TCP/IP networking protocol installed; Internet Explorer 6.0 or later.
596 ## -
-- 1
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic circuits
General subdivision Design and construction
-- Data processing.
9 (RLIN) 2078
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Logic design
General subdivision Data processing.
9 (RLIN) 2079
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element VHDL (Computer hardware description language)
9 (RLIN) 996
700 1# - ADDED ENTRY--PERSONAL NAME
Personal name Vranesic, Zvonko G.
9 (RLIN) 2080
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Source of acquisition Total Checkouts Full call number Barcode Date last seen Copy number Price effective from Koha item type
    Dewey Decimal Classification     Main library Main library General Stacks 01/26/2020 BAC_P   621.395 / BR.F 2008 002699 11/24/2019 1 11/24/2019 Books
    Dewey Decimal Classification     Main library Main library General Stacks 01/26/2020 AHRA-P   621.395 / BR.F 2008 002871 06/29/2021 2 11/24/2019 Books