Current Source Based Standard Cell Model for Accurate Timing Analysis of Combinational Logic Cells /
Mohamed Mahmoud Mohamed Ahmed Ismail
Current Source Based Standard Cell Model for Accurate Timing Analysis of Combinational Logic Cells / Mohamed Mahmoud Mohamed Ahmed Ismail - 2013 - 94 p. ill. 21 cm.
Supervisor: Rafik Guindi
Thesis (M.A.)—Nile University, Egypt, 2013 .
"Includes bibliographical references"
Contents:
Chapter 1: Introduction ................................................................................................................... 1
1.1. Classical STA Techniques ............................................................................................... 2
1.2. Motivation ........................................................................................................................ 2
1.3. Current Source Models..................................................................................................... 4
1.4. Thesis Organization.......................................................................................................... 6
Chapter 2: Existing Current Source Based Modeling Approaches for STA .................................. 7
2.1. Introduction ...................................................................................................................... 7
2.2. Blade and Razor Approach [18] ....................................................................................... 8
2.2.1. The Blade Model....................................................................................................... 8
2.2.2. The Blade Runtime Engine ..................................................................................... 10
2.2.3. Razor ....................................................................................................................... 10
2.2.4. Approach Pros and Cons ......................................................................................... 12
2.3. Analytical CSM Models for SIS and MIS [24] .............................................................. 12
2.3.1. The Model Structure ............................................................................................... 13
vii
2.3.2. Analytical Model for Non-Linear Idc ...................................................................... 14
2.3.3. Characterization of Capacitances ............................................................................ 15
2.3.4. Modeling MIS ......................................................................................................... 18
2.3.5. Computing the Transient Response ........................................................................ 19
2.3.6. Approach Pros and Cons ......................................................................................... 20
2.4. CSM Model Considering MIS and Stack Effect [27] .................................................... 20
2.4.1. CSM for SIS ............................................................................................................ 21
2.4.2. MIS and Stack Effect .............................................................................................. 21
2.4.3. MIS CSM ................................................................................................................ 23
2.4.4. Computing the Transient Response ........................................................................ 24
2.4.5. Approach Pros and Cons ......................................................................................... 24
2.5. A Multi-Port CSM for MIS [5] ...................................................................................... 25
2.5.1. The Model Structure ............................................................................................... 25
2.5.2. MCSM Characterization ......................................................................................... 26
2.5.3. Approach Pros and Cons ......................................................................................... 27
2.6. CSM Models for Combinational and Sequential Logic Cells [28] ................................ 27
2.6.1. CSM for Combinational Logic Cells ...................................................................... 28
2.6.2. CSM for Sequential Logic Cells ............................................................................. 28
2.6.3. Approach Pros and Cons ......................................................................................... 33
Chapter 3: The Proposed CSM ..................................................................................................... 34
viii
3.1. Introduction .................................................................................................................... 34
3.2. The Model Structure....................................................................................................... 35
3.3. Characterizing the Current Source Io(Vi,Vo) ................................................................... 36
3.4. Characterizing the Model Capacitances ......................................................................... 37
3.4.1. Characterizing CM(Vi,Vo) ........................................................................................ 37
3.4.2. Characterizing Co(Vi,Vo) ......................................................................................... 38
3.4.3. Characterizing Ci(Vi,Vo) .......................................................................................... 40
3.5. Computing the Output Transient Response ................................................................... 41
Chapter 4: Simulations and Results .............................................................................................. 44
4.1. Cell Delay Comparisons................................................................................................. 45
4.1.1. Cell Delay Comparisons for INVX0....................................................................... 45
4.1.2. Cell Delay Comparisons for NAND2X0 ................................................................ 50
4.1.3. Cell Delay Comparisons for NOR2X0 ................................................................... 59
4.1.4. Average Error in Cell Delay Comparisons ............................................................. 67
4.2. Output Waveforms Comparisons ................................................................................... 68
Chapter 5: Summary and Future Work ......................................................................................... 71
5.1. Summary ........................................................................................................................ 71
5.2. Conclusion ...................................................................................................................... 73
5.3. Future Work ................................................................................................................... 73
References ...........................
Abstract:
Timing verification is an essential process in nano-meter design. Therefore, static timing analysis (STA) is currently the main aspect of performance verification. Unlike timing simulation, STA requires only a single pass through the circuit to obtain the final delay; hence, STA has a linear run-time complexity with the circuit size. However, STA trades off its efficient run-time with a conservative estimate of the circuit delay. Traditional STA is based on lookup tables (LUT), where the logic cells are characterized for the cell delay and the output slew as a function of the input rise time and the output load capacitance. This characterization is done assuming that the input waveform can be described by a saturated ramp and the output load can be modeled by a single linear effective capacitance (Ceff).
However, in deep submicron technologies, the classical STA methods become insufficient to accurately characterize many significant challenges such as; nonlinear waveforms, nonlinear loads, and multiple input switching (MIS). So, the current trend in modern designs is to use current source based models (CSM) which are independent of the shape of the input signal and the output load. It depends on the values of the input and output voltages at a given time instant. Therefore, it overcomes the above-mentioned shortcomings of the traditional STA methods.
This thesis presents a novel CSM model for combinational logic cells, which can handle single input switching (SIS) signals. The proposed model can also handle cases of applying fast ramp input signals to cells with small output load capacitances. The experimental results show that the proposed model accurately captures the shape of the output waveform produced by ELDO simulations. Moreover, it produces more accurate stage delay than that obtained from the traditional standard cells lookup tables.
Text in English, abstracts in English.
MSD
Dissertation, Academic
621
Current Source Based Standard Cell Model for Accurate Timing Analysis of Combinational Logic Cells / Mohamed Mahmoud Mohamed Ahmed Ismail - 2013 - 94 p. ill. 21 cm.
Supervisor: Rafik Guindi
Thesis (M.A.)—Nile University, Egypt, 2013 .
"Includes bibliographical references"
Contents:
Chapter 1: Introduction ................................................................................................................... 1
1.1. Classical STA Techniques ............................................................................................... 2
1.2. Motivation ........................................................................................................................ 2
1.3. Current Source Models..................................................................................................... 4
1.4. Thesis Organization.......................................................................................................... 6
Chapter 2: Existing Current Source Based Modeling Approaches for STA .................................. 7
2.1. Introduction ...................................................................................................................... 7
2.2. Blade and Razor Approach [18] ....................................................................................... 8
2.2.1. The Blade Model....................................................................................................... 8
2.2.2. The Blade Runtime Engine ..................................................................................... 10
2.2.3. Razor ....................................................................................................................... 10
2.2.4. Approach Pros and Cons ......................................................................................... 12
2.3. Analytical CSM Models for SIS and MIS [24] .............................................................. 12
2.3.1. The Model Structure ............................................................................................... 13
vii
2.3.2. Analytical Model for Non-Linear Idc ...................................................................... 14
2.3.3. Characterization of Capacitances ............................................................................ 15
2.3.4. Modeling MIS ......................................................................................................... 18
2.3.5. Computing the Transient Response ........................................................................ 19
2.3.6. Approach Pros and Cons ......................................................................................... 20
2.4. CSM Model Considering MIS and Stack Effect [27] .................................................... 20
2.4.1. CSM for SIS ............................................................................................................ 21
2.4.2. MIS and Stack Effect .............................................................................................. 21
2.4.3. MIS CSM ................................................................................................................ 23
2.4.4. Computing the Transient Response ........................................................................ 24
2.4.5. Approach Pros and Cons ......................................................................................... 24
2.5. A Multi-Port CSM for MIS [5] ...................................................................................... 25
2.5.1. The Model Structure ............................................................................................... 25
2.5.2. MCSM Characterization ......................................................................................... 26
2.5.3. Approach Pros and Cons ......................................................................................... 27
2.6. CSM Models for Combinational and Sequential Logic Cells [28] ................................ 27
2.6.1. CSM for Combinational Logic Cells ...................................................................... 28
2.6.2. CSM for Sequential Logic Cells ............................................................................. 28
2.6.3. Approach Pros and Cons ......................................................................................... 33
Chapter 3: The Proposed CSM ..................................................................................................... 34
viii
3.1. Introduction .................................................................................................................... 34
3.2. The Model Structure....................................................................................................... 35
3.3. Characterizing the Current Source Io(Vi,Vo) ................................................................... 36
3.4. Characterizing the Model Capacitances ......................................................................... 37
3.4.1. Characterizing CM(Vi,Vo) ........................................................................................ 37
3.4.2. Characterizing Co(Vi,Vo) ......................................................................................... 38
3.4.3. Characterizing Ci(Vi,Vo) .......................................................................................... 40
3.5. Computing the Output Transient Response ................................................................... 41
Chapter 4: Simulations and Results .............................................................................................. 44
4.1. Cell Delay Comparisons................................................................................................. 45
4.1.1. Cell Delay Comparisons for INVX0....................................................................... 45
4.1.2. Cell Delay Comparisons for NAND2X0 ................................................................ 50
4.1.3. Cell Delay Comparisons for NOR2X0 ................................................................... 59
4.1.4. Average Error in Cell Delay Comparisons ............................................................. 67
4.2. Output Waveforms Comparisons ................................................................................... 68
Chapter 5: Summary and Future Work ......................................................................................... 71
5.1. Summary ........................................................................................................................ 71
5.2. Conclusion ...................................................................................................................... 73
5.3. Future Work ................................................................................................................... 73
References ...........................
Abstract:
Timing verification is an essential process in nano-meter design. Therefore, static timing analysis (STA) is currently the main aspect of performance verification. Unlike timing simulation, STA requires only a single pass through the circuit to obtain the final delay; hence, STA has a linear run-time complexity with the circuit size. However, STA trades off its efficient run-time with a conservative estimate of the circuit delay. Traditional STA is based on lookup tables (LUT), where the logic cells are characterized for the cell delay and the output slew as a function of the input rise time and the output load capacitance. This characterization is done assuming that the input waveform can be described by a saturated ramp and the output load can be modeled by a single linear effective capacitance (Ceff).
However, in deep submicron technologies, the classical STA methods become insufficient to accurately characterize many significant challenges such as; nonlinear waveforms, nonlinear loads, and multiple input switching (MIS). So, the current trend in modern designs is to use current source based models (CSM) which are independent of the shape of the input signal and the output load. It depends on the values of the input and output voltages at a given time instant. Therefore, it overcomes the above-mentioned shortcomings of the traditional STA methods.
This thesis presents a novel CSM model for combinational logic cells, which can handle single input switching (SIS) signals. The proposed model can also handle cases of applying fast ramp input signals to cells with small output load capacitances. The experimental results show that the proposed model accurately captures the shape of the output waveform produced by ELDO simulations. Moreover, it produces more accurate stage delay than that obtained from the traditional standard cells lookup tables.
Text in English, abstracts in English.
MSD
Dissertation, Academic
621